device/pci_ids, soc/intel/pantherlake: Add new PTL-H DID0

This patch adds new DID0 PCI device IDs for Intel PTL-H.

Additionally, updates the System Agent driver's `systemagent_ids`
list and Panther Lake SoC bootblock to support these new IDs.

Source: Intel PTL-FAS. Document Number 812562

BUG=b:347669091
TEST=Build fatcat and boot with Panther Lake SoC with newly added
MCH ID.

With patch, coreboot log:
`[DEBUG]  MCH: device id b004 (rev 00) is Pantherlake H`
`[DEBUG]  MCH: device id b00a (rev 00) is Pantherlake H`

Change-Id: I56e795696f661d88828d7549f856eee19c46c942
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84916
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>

src/include/device/pci_ids.h

@@ -4456,6 +4456,8 @@
 #define PCI_DID_INTEL_PTL_U_ID_1		0xb000
 #define PCI_DID_INTEL_PTL_H_ID_1		0xb001
 #define PCI_DID_INTEL_PTL_H_ID_2		0xb002
+#define PCI_DID_INTEL_PTL_H_ID_3		0xb004
+#define PCI_DID_INTEL_PTL_H_ID_4		0xb00a
 #define PCI_DID_INTEL_SNR_ID			0x09a2
 
 /* Intel SMBUS device Ids */

src/soc/intel/common/block/systemagent/systemagent.c

@@ -427,6 +427,8 @@ static const unsigned short systemagent_ids[] = {
 	PCI_DID_INTEL_PTL_U_ID_1,
 	PCI_DID_INTEL_PTL_H_ID_1,
 	PCI_DID_INTEL_PTL_H_ID_2,
+	PCI_DID_INTEL_PTL_H_ID_3,
+	PCI_DID_INTEL_PTL_H_ID_4,
 	PCI_DID_INTEL_LNL_M_ID,
 	PCI_DID_INTEL_LNL_M_ID_1,
 	PCI_DID_INTEL_MTL_M_ID,

src/soc/intel/pantherlake/bootblock/report_platform.c

@@ -31,6 +31,8 @@ static struct {
 	{ PCI_DID_INTEL_PTL_U_ID_1, "Pantherlake U" },
 	{ PCI_DID_INTEL_PTL_H_ID_1, "Pantherlake H" },
 	{ PCI_DID_INTEL_PTL_H_ID_2, "Pantherlake H" },
+	{ PCI_DID_INTEL_PTL_H_ID_3, "Pantherlake H" },
+	{ PCI_DID_INTEL_PTL_H_ID_4, "Pantherlake H" },
 };
 
 static struct {

src/soc/intel/pantherlake/chip.h

@@ -66,6 +66,8 @@ static const struct {
 	{ PCI_DID_INTEL_PTL_U_ID_1, PTL_U_1_CORE, TDP_15W },
 	{ PCI_DID_INTEL_PTL_H_ID_1, PTL_H_1_CORE, TDP_25W },
 	{ PCI_DID_INTEL_PTL_H_ID_2, PTL_H_3_CORE, TDP_45W },
+	{ PCI_DID_INTEL_PTL_H_ID_3, PTL_H_1_CORE, TDP_25W },
+	{ PCI_DID_INTEL_PTL_H_ID_4, PTL_H_1_CORE, TDP_25W },
 };
 
 /* Types of display ports */