soc/intel/mtl to xeon_sp: Explicitly include static.h for config_of_soc

As per commit 8651731537 ("sconfig: Move config_of_soc from device.h
to static.h"), sources that require access to the devicetree should
directly include static.h so that it can be removed from device.h,
eliminating unnecessary dependencies on static.h for files that only
need the types and function declarations in device.h.

Change-Id: I3c118a707dfe7bb8932606f30eae52ef0b4c9efe
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>

src/soc/intel/meteorlake/acpi.c

@@ -20,6 +20,7 @@
 #include <soc/pm.h>
 #include <soc/soc_chip.h>
 #include <soc/systemagent.h>
+#include <static.h>
 #include <types.h>
 
 /*

src/soc/intel/meteorlake/chip.c

@@ -24,6 +24,7 @@
 #include <soc/ramstage.h>
 #include <soc/soc_chip.h>
 #include <soc/tcss.h>
+#include <static.h>
 
 #if CONFIG(HAVE_ACPI_TABLES)
 const char *soc_acpi_name(const struct device *dev)

src/soc/intel/meteorlake/cpu.c

@@ -21,6 +21,7 @@
 #include <soc/pci_devs.h>
 #include <soc/soc_chip.h>
 #include <soc/soc_info.h>
+#include <static.h>
 
 bool cpu_soc_is_in_untrusted_mode(void)
 {

src/soc/intel/meteorlake/espi.c

@@ -13,6 +13,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pcr_ids.h>
 #include <soc/soc_chip.h>
+#include <static.h>
 
 void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
 {

src/soc/intel/meteorlake/fsp_params.c

@@ -32,6 +32,7 @@
 #include <soc/ramstage.h>
 #include <soc/soc_chip.h>
 #include <soc/soc_info.h>
+#include <static.h>
 #include <stdlib.h>
 #include <string.h>
 #include <types.h>

src/soc/intel/meteorlake/pmc.c

@@ -15,6 +15,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/soc_chip.h>
+#include <static.h>
 #include <stdint.h>
 #include <bootstate.h>
 

src/soc/intel/meteorlake/pmutil.c

@@ -24,6 +24,7 @@
 #include <soc/pm.h>
 #include <soc/smbus.h>
 #include <soc/soc_chip.h>
+#include <static.h>
 #include <types.h>
 
 /*

src/soc/intel/meteorlake/romstage/fsp_params.c

@@ -26,6 +26,7 @@
 #include <soc/romstage.h>
 #include <soc/soc_chip.h>
 #include <soc/soc_info.h>
+#include <static.h>
 #include <string.h>
 #include <ux_locales.h>
 

src/soc/intel/meteorlake/systemagent.c

@@ -12,6 +12,7 @@
 #include <soc/iomap.h>
 #include <soc/soc_chip.h>
 #include <soc/systemagent.h>
+#include <static.h>
 
 /*
  * SoC implementation

src/soc/intel/meteorlake/tcss.c

@@ -2,6 +2,7 @@
 
 #include <intelblocks/tcss.h>
 #include <soc/soc_chip.h>
+#include <static.h>
 
 const struct soc_tcss_ops tcss_ops = {
 	.configure_aux_bias_pads = ioe_tcss_configure_aux_bias_pads_sbi,

src/soc/intel/pantherlake/acpi.c

@@ -20,6 +20,7 @@
 #include <soc/pm.h>
 #include <soc/soc_chip.h>
 #include <soc/systemagent.h>
+#include <static.h>
 #include <types.h>
 
 /*

src/soc/intel/pantherlake/chip.c

@@ -24,6 +24,7 @@
 #include <soc/ramstage.h>
 #include <soc/soc_chip.h>
 #include <soc/tcss.h>
+#include <static.h>
 
 #if CONFIG(HAVE_ACPI_TABLES)
 const char *soc_acpi_name(const struct device *dev)

src/soc/intel/pantherlake/cpu.c

@@ -20,6 +20,7 @@
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
 #include <soc/soc_chip.h>
+#include <static.h>
 
 bool cpu_soc_is_in_untrusted_mode(void)
 {

src/soc/intel/pantherlake/espi.c

@@ -13,6 +13,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pcr_ids.h>
 #include <soc/soc_chip.h>
+#include <static.h>
 
 void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
 {

src/soc/intel/pantherlake/fsp_params.c

@@ -16,6 +16,7 @@
 #include <soc/intel/common/vbt.h>
 #include <soc/pcie.h>
 #include <soc/ramstage.h>
+#include <static.h>
 
 #define MAX_ONBOARD_PCIE_DEVICES 256
 

src/soc/intel/pantherlake/pmc.c

@@ -15,6 +15,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/soc_chip.h>
+#include <static.h>
 #include <stdint.h>
 
 #define PMC_HID		"INTC1026"

src/soc/intel/pantherlake/pmutil.c

@@ -24,6 +24,7 @@
 #include <soc/pm.h>
 #include <soc/smbus.h>
 #include <soc/soc_chip.h>
+#include <static.h>
 #include <types.h>
 
 /*

src/soc/intel/pantherlake/romstage/fsp_params.c

@@ -9,6 +9,7 @@
 #include <soc/msr.h>
 #include <soc/pcie.h>
 #include <soc/romstage.h>
+#include <static.h>
 
 #define FSP_CLK_NOTUSED		0xff
 #define FSP_CLK_LAN		0x70

src/soc/intel/pantherlake/systemagent.c

@@ -12,6 +12,7 @@
 #include <soc/iomap.h>
 #include <soc/soc_chip.h>
 #include <soc/systemagent.h>
+#include <static.h>
 
 /*
  * SoC implementation

src/soc/intel/skylake/acpi.c

@@ -17,6 +17,7 @@
 #include <soc/pm.h>
 #include <soc/ramstage.h>
 #include <soc/systemagent.h>
+#include <static.h>
 #include <string.h>
 #include <types.h>
 

src/soc/intel/skylake/bootblock/pch.c

@@ -18,6 +18,7 @@
 #include <soc/pcr_ids.h>
 #include <soc/pm.h>
 #include <soc/pmc.h>
+#include <static.h>
 #include "../chip.h"
 
 #define PCR_DMI_ACPIBA		0x27B4

src/soc/intel/skylake/chip.c

@@ -28,6 +28,7 @@
 #include <soc/ramstage.h>
 #include <soc/systemagent.h>
 #include <soc/usb.h>
+#include <static.h>
 #include <string.h>
 #include <types.h>
 

src/soc/intel/skylake/cpu.c

@@ -21,6 +21,7 @@
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 #include <soc/systemagent.h>
+#include <static.h>
 #include <types.h>
 
 #include "chip.h"

src/soc/intel/skylake/fadt.c

@@ -3,6 +3,7 @@
 #include <acpi/acpi.h>
 #include <soc/iomap.h>
 #include <soc/pm.h>
+#include <static.h>
 #include "chip.h"
 
 void soc_fill_fadt(acpi_fadt_t *fadt)

src/soc/intel/skylake/lpc.c

@@ -10,6 +10,7 @@
 #include <soc/iomap.h>
 #include <soc/pcr_ids.h>
 #include <soc/intel/common/block/lpc/lpc_def.h>
+#include <static.h>
 
 #include "chip.h"
 

src/soc/intel/skylake/pmc.c

@@ -11,6 +11,7 @@
 #include <intelblocks/rtc.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
+#include <static.h>
 
 #include "chip.h"
 

src/soc/intel/skylake/pmutil.c

@@ -24,6 +24,7 @@
 #include <soc/pmc.h>
 #include <soc/smbus.h>
 #include <security/vboot/vbnv.h>
+#include <static.h>
 
 #include "chip.h"
 

src/soc/intel/skylake/romstage/fsp_params.c

@@ -10,6 +10,7 @@
 #include <soc/pci_devs.h>
 #include <soc/romstage.h>
 #include <soc/soc_chip.h>
+#include <static.h>
 
 static void cpu_flex_override(FSP_M_CONFIG *m_cfg)
 {

src/soc/intel/skylake/systemagent.c

@@ -12,6 +12,7 @@
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
 #include <soc/systemagent.h>
+#include <static.h>
 #include <types.h>
 #include "chip.h"
 

src/soc/intel/tigerlake/acpi.c

@@ -19,6 +19,7 @@
 #include <soc/pm.h>
 #include <soc/soc_chip.h>
 #include <soc/systemagent.h>
+#include <static.h>
 
 /*
  * List of supported C-states in this processor.

src/soc/intel/tigerlake/bootblock/pch.c

@@ -27,6 +27,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pcr_ids.h>
 #include <soc/pm.h>
+#include <static.h>
 
 #if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
 #define PCR_PSF3_TO_SHDW_PMC_REG_BASE	0x1000

src/soc/intel/tigerlake/chip.c

@@ -16,6 +16,7 @@
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 #include <soc/soc_chip.h>
+#include <static.h>
 
 #if CONFIG(HAVE_ACPI_TABLES)
 const char *soc_acpi_name(const struct device *dev)

src/soc/intel/tigerlake/cpu.c

@@ -20,6 +20,7 @@
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
 #include <soc/soc_chip.h>
+#include <static.h>
 #include <types.h>
 
 bool cpu_soc_is_in_untrusted_mode(void)

src/soc/intel/tigerlake/espi.c

@@ -20,6 +20,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pcr_ids.h>
 #include <soc/soc_chip.h>
+#include <static.h>
 
 void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
 {

src/soc/intel/tigerlake/fsp_params.c

@@ -27,6 +27,7 @@
 #include <soc/ramstage.h>
 #include <soc/soc_chip.h>
 #include <soc/tcss.h>
+#include <static.h>
 #include <string.h>
 #include <types.h>
 

src/soc/intel/tigerlake/pmc.c

@@ -20,6 +20,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/soc_chip.h>
+#include <static.h>
 #include <bootstate.h>
 
 #define PMC_HID		"INTC1026"

src/soc/intel/tigerlake/pmutil.c

@@ -30,6 +30,7 @@
 #include <soc/smbus.h>
 #include <soc/soc_chip.h>
 #include <security/vboot/vbnv.h>
+#include <static.h>
 
 /*
  * SMI

src/soc/intel/tigerlake/romstage/fsp_params.c

@@ -16,6 +16,7 @@
 #include <soc/pci_devs.h>
 #include <soc/romstage.h>
 #include <soc/soc_chip.h>
+#include <static.h>
 #include <string.h>
 
 static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,

src/soc/intel/tigerlake/systemagent.c

@@ -17,6 +17,7 @@
 #include <soc/iomap.h>
 #include <soc/soc_chip.h>
 #include <soc/systemagent.h>
+#include <static.h>
 
 /*
  * SoC implementation

src/soc/intel/xeon_sp/acpi.c

@@ -9,6 +9,7 @@
 #include <soc/pci_devs.h>
 #include <soc/util.h>
 #include <southbridge/intel/common/acpi_pirq_gen.h>
+#include <static.h>
 #include <stdint.h>
 #include <stdio.h>
 #include <stdlib.h>

src/soc/intel/xeon_sp/cpx/romstage.c

@@ -13,6 +13,7 @@
 #include <soc/pci_devs.h>
 #include <soc/intel/common/smbios.h>
 #include <soc/soc_util.h>
+#include <static.h>
 #include <string.h>
 
 #include "chip.h"

src/soc/intel/xeon_sp/lpc.c

@@ -4,6 +4,7 @@
 #include <intelblocks/lpc_lib.h>
 #include <soc/iomap.h>
 #include <soc/pcr_ids.h>
+#include <static.h>
 
 #include <chip.h>
 

src/soc/intel/xeon_sp/skx/romstage.c

@@ -4,6 +4,7 @@
 #include <intelblocks/rtc.h>
 #include <soc/romstage.h>
 #include <soc/soc_util.h>
+#include <static.h>
 
 #include "chip.h"
 

src/soc/intel/xeon_sp/spr/romstage.c

@@ -18,6 +18,7 @@
 #include <soc/romstage.h>
 #include <soc/pci_devs.h>
 #include <soc/soc_pch.h>
+#include <static.h>
 #include <string.h>
 #include <soc/config.h>
 #include <soc/soc_util.h>