soc/intel/{adl, mtl, ptl}: Drop CLFLUSH (X86_CLFLUSH_CAR) config

This patch drops the X86_CLFLUSH_CAR config from the latest Intel SoCs
(ADL, MTL, PTL) following the switch to WC (Write-Combining) MTRR type
for the RAMTOP range.

Previously, with WB (Write-Back) caching for RAMTOP, CLFLUSH was
crucial to ensure data consistency, as WB caches both reads and writes.
However, since the RAMTOP range now relies on WC MTRR, the role of
CLFLUSH becomes less critical.

Removing CLFLUSH in this scenario can improve performance, as it avoids
unnecessary cache invalidations.

BUG=b:373290479
TEST=Able to build and boot google/trulo.

Change-Id: I3631a58ba03cd2fbe8821bc89b1ca7226c2f0fd4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85028
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>

src/soc/intel/alderlake/Kconfig

@@ -96,7 +96,6 @@ config SOC_INTEL_ALDERLAKE
 	select UDK_202111_BINDING if SOC_INTEL_ALDERLAKE_PCH_N
 	select UDK_202005_BINDING if !SOC_INTEL_ALDERLAKE_PCH_N && !SOC_INTEL_RAPTORLAKE
 	select VBOOT_LIB
-	select X86_CLFLUSH_CAR
 	help
 	  Intel Alderlake support. Mainboards should specify the PCH
 	  type using the `SOC_INTEL_ALDERLAKE_PCH_*` options instead

src/soc/intel/meteorlake/Kconfig

@@ -102,7 +102,6 @@ config SOC_INTEL_METEORLAKE
 	select TSC_MONOTONIC_TIMER
 	select UDELAY_TSC
 	select UDK_202302_BINDING
-	select X86_CLFLUSH_CAR
 	select X86_INIT_NEED_1_SIPI
 	select INTEL_KEYLOCKER
 	help

src/soc/intel/pantherlake/Kconfig

@@ -105,7 +105,6 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select UDELAY_TSC
 	select UDK_202302_BINDING
 	select USE_X86_64_SUPPORT
-	select X86_CLFLUSH_CAR
 	select X86_INIT_NEED_1_SIPI
 	help
 	  Intel Pantherlake support. Mainboards should specify the SoC