mb/google/fatcat: Add ISH support with FW_CONFIG toggle

This patch adds support for the Integrated Sensor Hub (ISH) on the
Fatcat mainboard.

ISH can be enabled or disabled via FW_CONFIG bit 24. This allows for
flexible configuration depending on the system requirements.

The GPIO configuration for ISH is also updated based on CBI settings,
ensuring correct initialization and communication.

Verified that the device tree correctly probes ISH based on the
FW_CONFIG setting:

*   FW_CONFIG with bit 24 set: ISH is probed successfully.
*   FW_CONFIG with bit 24 cleared: ISH is not probed.

BUG=b:370984186
TEST=Verified ISH probing behavior with different FW_CONFIG settings
using CBI.

Change-Id: I1a9734139a49be982a7dd43d5afd92e7fea6b29c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Subrata Banik 2024-11-05 12:44:20 +05:30
commit 7101c166fa
4 changed files with 46 additions and 16 deletions

View file

@ -40,6 +40,7 @@ config BOARD_GOOGLE_BASEBOARD_FATCAT
def_bool n
select BOARD_GOOGLE_FATCAT_COMMON
select CHROMEOS_WIFI_SAR if CHROMEOS
select DRIVERS_INTEL_ISH
select DRIVERS_INTEL_USB4_RETIMER
select HAVE_SLP_S0_GATE
select MAINBOARD_HAS_CHROMEOS

View file

@ -453,6 +453,24 @@ static const struct pad_config touchpad_i2c_disable_pads[] = {
PAD_NC(GPP_F18, NONE),
};
static const struct pad_config ish_disable_pads[] = {
/* GPP_D05: NC */
PAD_NC(GPP_D05, NONE),
/* GPP_D06: NC */
PAD_NC(GPP_D06, NONE),
/* GPP_E05: NC */
PAD_NC(GPP_E05, NONE),
};
static const struct pad_config ish_enable_pads[] = {
/* GPP_D05: ISH_UART0_RXD */
PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2),
/* GPP_D06: ISH_UART0_TXD */
PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2),
/* GPP_E05: ISH_GP_7_SNSR_HDR */
PAD_CFG_NF(GPP_E05, NONE, DEEP, NF4),
};
void fw_config_configure_pre_mem_gpio(void)
{
if (!fw_config_is_provisioned()) {
@ -578,6 +596,11 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
else
GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_disable_pads);
if (fw_config_probe(FW_CONFIG(ISH, ISH_DISABLE)))
GPIO_PADBASED_OVERRIDE(padbased_table, ish_disable_pads);
else
GPIO_PADBASED_OVERRIDE(padbased_table, ish_enable_pads);
/* NOTE: disable PEG (x8 slot) and x4 slot wake for now */
GPIO_PADBASED_OVERRIDE(padbased_table, peg_x4slot_wake_disable_pads);
}

View file

@ -163,14 +163,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPP_D03, 1, PLTRST),
/* GPP_D04: IMGCLKOUT_0 */
PAD_CFG_NF(GPP_D04, NONE, DEEP, NF1),
/* GPP_D05: ISH_SPI_CS_N_SNSR_HDR */
PAD_CFG_NF(GPP_D05, NONE, DEEP, NF3),
/* GPP_D06: ISH_SPI_CLK_SNSR_HDR */
PAD_CFG_NF(GPP_D06, NONE, DEEP, NF3),
/* GPP_D07: ISH_SPI_MISO_SNSR_HDR */
PAD_CFG_NF(GPP_D07, NONE, DEEP, NF3),
/* GPP_D08: ISH_SPI_MOSI_SNSR_HDR */
PAD_CFG_NF(GPP_D08, NONE, DEEP, NF3),
/* GPP_D07: NC */
PAD_NC(GPP_D07, NONE),
/* GPP_D08: NC */
PAD_NC(GPP_D08, NONE),
/* GPP_D09: PEG_SLOT_RST_N */
PAD_CFG_GPO(GPP_D09, 1, PLTRST),
/* GPP_D10: HDA_BCLK */
@ -212,8 +208,6 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI_SCI_LOW(GPP_E02, NONE, DEEP, LEVEL),
/* GPP_E03: M2_GEN5_SSD_RESET_N */
PAD_CFG_GPO(GPP_E03, 1, PLTRST),
/* GPP_E05: ISH_GP_7_SNSR_HDR */
PAD_CFG_NF(GPP_E05, NONE, DEEP, NF4),
/* GPP_E06: SECURE_CAM_SW */
PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, PLTRST, LEVEL, ACPI),
/* GPP_E07: Not used */
@ -274,8 +268,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_F07, NONE, DEEP, NF2),
/* GPP_F08: TCH_PNL1_PWR_EN */
PAD_CFG_GPO(GPP_F08, 1, PLTRST),
/* GPP_F09: ISH_INT_GP11_CVS */
PAD_CFG_NF(GPP_F09, NONE, DEEP, NF4),
/* GPP_F09: NC */
PAD_NC(GPP_F09, NONE),
/* GPP_F10: PEG_SLOT_PWR_EN_N */
PAD_CFG_GPO(GPP_F10, 0, PLTRST),
/* GPP_F11: MOD_TCSS2_TYP_A_VBUS_EN */
@ -329,10 +323,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
/* GPP_H13: CPU_C10_GATE_N_R */
PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
/* GPP_H14: ISH_I3C1_SDA_SNSR_HDR */
PAD_CFG_NF(GPP_H14, NONE, DEEP, NF4),
/* GPP_H15: ISH_I3C1_SCL_SNSR_HDR */
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF4),
/* GPP_H14: NC */
PAD_NC(GPP_H14, NONE),
/* GPP_H15: NC */
PAD_NC(GPP_H15, NONE),
/* GPP_H16: WWAN_PWREN */
PAD_CFG_GPO(GPP_H16, 1, PLTRST),
/* GPP_H17: MIC MUTE LED */

View file

@ -62,6 +62,10 @@ fw_config
option WFC_MIPI 1
option WFC_USB 2
end
field ISH 24
option ISH_DISABLE 0
option ISH_ENABLE 1
end
end
chip soc/intel/pantherlake
@ -227,6 +231,14 @@ chip soc/intel/pantherlake
end
end
device ref ish on
probe ISH ISH_ENABLE
chip drivers/intel/ish
register "add_acpi_dma_property" = "true"
device generic 0 on end
end
end
device ref xhci on
chip drivers/usb/acpi
device ref xhci_root_hub on