This commit enables the Dynamic Platform and Thermal Framework (DPTF)
for the fatcat board.
DPTF is a system management framework that allows the board to
dynamically adjust its power and thermal settings based on the system
load and thermal conditions. This can help to improve the board's
performance and battery life.
The following changes were made to enable DPTF:
- Added the Intel DPTF driver to the board's Kconfig file.
- Overrode the default DPTF settings in the fatcat variant
overridetree.cb file.
- Enabled the DPTF policy on the baseboard.
Change-Id: I2b5042795acee3e261765ca4c392d15ef7f5ca97
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85457
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Enable the DRIVERS_GENERIC_BAYHUB_LV2 Kconfig option to apply
errata for the Bayhub PCIe-based SD controller (device ID 0x8621).
BUG=b:376019977
TEST=Built and booted google/fatcat with a functional x1 slot.
Change-Id: Iebc5bb73d895e8b20c47a924c6665c6ad289d1c4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The following GPIOs are already implemented in fw_config.c based on
CBI values:
- GPP_A08: X1_PCIE_SLOT_PWR_EN
- GPP_B25: X1_SLOT_WAKE_N
- GPP_D19: X1_DT_PCIE_RST_N
This change removes the redundant GPIO definitions from gpio.c.
BUG=b:376019977
TEST=Able to build and boot google/fatcat with functional x1 slot.
Change-Id: I56c6fd3ea8b9e58933548543d195621da94c882e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch corrects the calculation of the _ADR value for the Intel UFS
controller in the `soc/ufs.h` header file.
The previous calculation incorrectly included a hardcoded value (0x0007)
in the lower bits of the _ADR. This is not in line with the Panther Lake
EDS specification (doc: 815002)
BUG=b:382243957
TEST=Able to build and boot google/fatcat.
> iasl -d /sys/firmware/acpi/tables/DSDT
Device (UFS)
{
Name (_ADR, 0x00170000) // _ADR: Address
Name (_DDN, "UFS Controller") // _DDN: DOS Device Name
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
Change-Id: I889403e4d33efb5818fec06d773b5aec0a74d0b3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85528
Reviewed-by: Divagar Mohandass <divagar.mohandass@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Currently, with default speed auto the Wifi 7 M.2 module will not work under speed Gen3. This is due to driver iwlwifi for wifi7 is not stable and decreasing the speed to Gen2 gets the card working without any downsides, as the Wifi 7 speed can be serviced by 5 GT/s.
BUG=b:376156567
TEST=Boot to OS and then check link speed.
Use command: lspci -s 02:00.0 -vv | grep 'LnkSta'
Before
LnkSta: Speed 8GT/s (downgraded), Width x1
After
LnkSta: Speed 5GT/s (downgraded), Width x1
Change-Id: I9e8a02061251f73ee5ec2299e62fa423ff4b0965
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85533
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
pcr_read16(PID_ITSS, itss_soc_get_on_chip_dev_pir(dev)) returns
the register content and should not be compared with
PCI_ITSS_PIR(0) which is an address offset. By now, we assume the
returned PIR is always effective and usable.
Change-Id: I2e61629bdcdea33f260bfbc47f22d40d9a869c6b
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85284
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: <yuchi.chen@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add const qualifer for itss_get_on_chip_dev_pirq and
itss_soc_get_on_chip_dev_pir so that these ops could be used for
both struct device * input and const struct device * input.
Change-Id: I65b4de3f51b109bfcabfaa0ebe47a22bdd69d1a0
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85283
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <yuchi.chen@intel.com>
If CHIPSET_LOCKDOWN_COREBOOT is selected, lpc_lockdown_config() will
be executed in common pch/lockdown firstly. Remove xeon_sp layer
lpc_lockdown_config() to avoid duplication.
The duplicated part are in src/soc/intel/common/pch/lockdown/lockdown.c:
static void platform_lockdown_config(void *unused)
{
int chipset_lockdown;
chipset_lockdown = get_lockdown_config();
/* SPI lock down configuration */
fast_spi_lockdown_cfg(chipset_lockdown);
/* LPC/eSPI lock down configuration */
lpc_lockdown_config(chipset_lockdown);
...
}
Change-Id: Ibec389a6d55c7885def6896a0ea435514b75a323
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85286
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Drop function fast_spi_set_vcl as the same code already exists
as fast_spi_vscc0_lock() and is already run on xeon_sp.
Change-Id: I86180c209e2d550c2bac3ace9cc344eabf950af0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
acpigen_write_PRT_pre_routed should support _PRT reporting for
both domains and PCI root ports.
TESTED=Build and boot on intel/avenuecity CRB
_PRT will be correctly reported and IRQ routing missing error in
dmesg will disappear
[ 40.406496] pcieport 0000:14:08.0: can't derive routing for PCI INT A
[ 40.413799] pci 0000:17:00.0: PCI INT A: no GSI
[ 40.418965] pcieport 0000:14:08.0: can't derive routing for PCI INT A
[ 40.426272] ast 0000:18:00.0: PCI INT A: no GSI
Change-Id: I07b9ce7b698a0bad30f0a20998a6543101d12542
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85151
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: <yuchi.chen@intel.com>
PCI devices not pre-routed will have their interrupt line left as
0. Skip these devices in _PRT reporting.
TESTED=Build and boot on intel/avenuecity CRB
Change-Id: I3d51b75eb0fd1c4ca877f6ac884de2742e7f9630
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85152
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: <yuchi.chen@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 8fb91783ffa9:
2024-08-23 14:45:12 +0200 - (Merge "fix(intel): add in missing ECC register" into integration)
to commit id 15e5c6c91d48:
2024-12-05 16:00:37 +0100 - (Merge changes I00d2de7b,I5ec82646 into integration)
This brings in 512 new commits.
Change-Id: I18b5bae0f48b2794a40d8c9e9cba8c69639669f6
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
The issue does not occur on Karis due to different WIFI module type
with current projects, Karis is using M.2 (none solder down version).
The decision to set PCIe root port 4 speed to Gen2 is based on experiment setup for b/374205496 and analysis results in #102.
BUG=b:374205496
TEST=Boot to OS and then check link speed.
Use command: lspci -vv | grep 'LnkSta'
Before
LnkSta: Speed 8GT/s (downgraded), Width x1
After
LnkSta: Speed 5GT/s (downgraded), Width x1
Change-Id: Ife2b60e78f943545fabd7095bd00d22704587aba
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch corrects the conditional inclusion of the `ufs.asl` file in
the southbridge ACPI configuration.
Previously, the inclusion of `ufs.asl` was incorrectly dependent on the
`MAINBOARD_USES_IFD_GBE_REGION` Kconfig option. This prevented the UFS
ACPI entry from being included in the DSDT when
`MAINBOARD_USES_IFD_GBE_REGION` was disabled, causing issues with
booting from UFS media.
This commit fixes the issue by ensuring that `ufs.asl` is included
based on the `SOC_INTEL_PANTHERLAKE_U_H` Kconfig option, which correctly
reflects the presence of UFS hardware.
This change ensures that the UFS ACPI device is correctly enumerated and
available to the operating system.
BUG=b:382243957
TEST=Able to verify UFS ACPI device is available inside DSDT table.
Change-Id: Ic8e87c57dd2db30f0ba13ac0a9f7fd2db877039a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add support for the optional TPM. When GPP_A22 is low a TPM is
installed.
TEST: Found a working TPM 2.0 SLB9670 on ocp/tiogapass.
Change-Id: I970033981a265eb0094bc91fc070487b34972a5a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85510
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CPX uses the same PCH as SKX does, thus it has the same ACPI timer
timer and PM2 control fields as SKX.
Copy the code from skx to cpx to reduce code differences. Allows to
merge both codebases into one.
Change-Id: I92fc63a6655fb915b2c06273c3259dddfb93e8bb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85508
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
None of the supported mainboards have a 8042 compatible chip,
thus drop it from the common code.
When such board is added it can update fadt->iapc_boot_arch
by installing a mainboard_fill_fadt() method.
Change-Id: I40cafcec57dd49399ce449700c81a1f27c1ded99
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85507
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Both CPX and SKX always enable EIST, thus the generic
generate_p_state_entries() method can be used to generate _PSS.
This also reduces code differences between skx and cpx and allows
to merge both codebases into one.
Change-Id: Ic7b03eef9498f2c442745119b24fb8b5c6169a08
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The board has 24 slots for DDR4 ECC RDIMMs and it has 2 CPU sockets,
where each is connected to 12 DIMMs. Every socket supports up to
6 channels, thus every channel is connected to 2 DIMMs.
Implement mainboard_dimm_slot_exists accordingly to advertise all slots
as SMBIOS type 17.
TEST: Found all installed DIMMs advertised through SMBIOS on
ocp/tiogapass.
Change-Id: I31cb4a89aa11258ac04eb69a0e9c86f258280484
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85318
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Do not use a define for a PCI register to lock a MSR.
The defines will be moved in the following commit to it's own header,
preventing the use in CPX CPU init.
Change-Id: I76a8ae13dbd942291aacbb4bd84140be156bc563
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move CPU init closer to other SoC and CPX.
FSP-S only is aware of socket 0, thus all cores must rerun all
settings already done by FSP, in order to set up socket 1 as well.
FSP sets the following on socket0:
- Set BIT20 in MSR_VR_MISC_CONFIG
- Set LTR_IIO_DISABLE in MSR_POWER_CTL
Lock the following MSRs:
- MSR_SNC_CONFIG
- MSR_CONFIG_TDP_CONTROL
- MSR_FEATURE_CONFIG
- MSR_TURBO_ACTIVATION_RATIO
Also do the following as done on other SoCs:
- Configure VMX and lock it
- Enable LAPIC TPRs (fixes MWAIT support)
- Honor CONFIG_SET_MSR_AESNI_LOCK_BIT
- Set TCC thermal target as set in devicetree
Fixes 8 second wakeup time from LAPIC interrupts when in MWAIT.
TEST: Booted on ocp/tiogapass to Linux 6.9 with all cores in
ACPI C6, no boot delay or hung tasks could be found.
Change-Id: If08ef5150b104b0c2329fcb64a0476ce641c831c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85289
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On platforms with multiple IOAPICs the GSI base must not be
linear, which is currently assumed by acpi_create_madt_ioapic_from_hw().
Integrate the existing struct device DEVICE_PATH_IOAPIC type and allow
to assign custom GSI bases for each IOAPIC. Write out the IOAPIC devices
into the MADT table if any.
For now, since no platform adds IOAPIC devices, the existing behaviour
remains the same. Allows to get rid of soc_get_ioapic_info().
Change-Id: Ie13d4f5c4f0704f0935974f90e5b7cf24e94aab3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The CSE MKHI_BUP_COMMON_GET_BOOT_PERF_DATA command is also implemented
in non-Lite CSE SKUs. Original CL [1] adding this feature also says
that, but at that point the feature was validated for CSE Lite only.
Move cse_get_boot_performance_data() to shared blk/cse/telemetry.c to
have it compile for mainboards without CSE Lite.
TEST=Boot NovaCustom V540TU (MTL-P / ME Consumer) with
SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 selected and check `cbmem -t`:
990:CSME ROM started execution 0
944:CSE sent 'Boot Stall Done' to PMC 34,000
945:CSE started to handle ICC configuration 172,000 (138,000)
946:CSE sent 'Host BIOS Prep Done' to PMC 172,000 (0)
947:CSE received 'CPU Reset Done Ack sent' from PMC 314,000 (142,000)
991:Die Management Unit (DMU) load completed 360,000 (46,000)
0:1st timestamp 385,844 (25,844)
11:start of bootblock 398,796 (12,952)
12:end of bootblock 402,099 (3,302)
[...]
[1]: https://review.coreboot.org/c/coreboot/+/59507
Change-Id: I3a5b1abd282af9af33cef2371719df4133684a2e
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
This change fixes building NovaCustom V540TU, which previously errored
out due to missing MISCCFG_GPIO_PM_CONFIG_BITS definition.
Replace soc/gpio_defs.h with gpio.h which includes everything we need,
same as it was done for ADL in change 71266, and other SoCs.
TEST=Build and boot NovaCustom V540TU
Change-Id: I52a495f696258fc63752dd8e66e318e144bb768e
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This change adds soundwire codec addresses in the devicetree to
calculate addresses for the ACPI table instead of previous kconfig which
allows single board to select multiple soundwire codecs at runtime
based on FW_CONFIG.
BUG=b:368495490
TEST=build coreboot image and boot on google fatcat. Disassemble
SSDT and confirm ACPI entries are correct for alc7xx device.
Change-Id: I3322ae2d106d3628dbf627aacf999056d82ee7a9
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Signed-off-by: Naveen M <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85440
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
- Use common config DRIVERS_SOUNDWIRE_ALC_BASE_7XX for ALC7xx variants
- Introduce soundwire codec address in soundwire chip.h to calculate
device address for acpi table based on overridetree.
- Update devicetree and Kconfig to use common config.
BUG=b:368495490
TEST=build coreboot image and boot on Intel RVP board. Disassemble
SSDT and confirm ACPI entries are correct for alc7xx device.
Change-Id: I5953d0fcb7b15368888901f88c5616757ac42877
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Signed-off-by: Naveen M <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85282
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This patch updates the flash layout for Fatcat variants to ensure
the flash layout is in alignment with the previous generation CrOS
devices like Rex.
SI_ALL: 9MB -> 8MB
SI_BIOS: 23MB -> 24MB
BUG=b:382247229
TEST=Able to build and boot google/fatcat.
Change-Id: I716fae09dee0c05b8b840dc80647d7959aa03a50
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit enhances the SMBIOS Type 4 table by populating the "serial
number" field with the unique SoC QDF information retrieved via PMC
IPC.
This improvement provides more accurate and detailed processor
information for Panther Lake SoCs and onwards, aiding in:
- System identification
- Diagnostics
- Asset management
Previously, the serial number field was not populated.
TEST=Able to build and boot google/fatcat.
Example of SMBIOS Type 4 output:
Before this commit:
Serial Number: Not Specified
Asset Tag: Not Specified
Part Number: Not Specified
After this commit:
Serial Number: ABCD (Example SoC QDF information)
Asset Tag: Not Specified
Part Number: Not Specified
Change-Id: I38a0bb0e44c619393b8f058ae30fbf2f9719b724
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit introduces a new function,
`retrieve_soc_qdf_info_via_pmc_ipc()`, to retrieve the SoC QDF
information string using the PMC IPC mechanism.
This function allows for more flexible use of the SoC QDF information,
enabling its use in various data structures like the SMBIOS Type 4
table.
The existing `pmc_dump_soc_qdf_info()` function is updated to use this
new function to retrieve the QDF information before printing it.
TEST=Able to build and boot google/fatcat.
Change-Id: I91ccf8aae4be9e9bbcad8ef2f422b88edef66376
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Add the MEMMAP_DIMM_DEVICE_INFO_STRUCT for skylake_sp and let common
code fill in the SMBIOS type 17 entries for all slots and found DIMMs.
This also allows to build dimm.c unconditionally on all xeon_sp socs.
Test: On ocp/tiogapass all DIMMs and slots are visible in SMBIOS.
Change-Id: I686b1e3ef946240785111f86a5f23a109a6a52ad
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Fix debug prints that use non-thread safe dev_path(). Since the code
is part of MPinit, it's using multiple threads and one threads modifies
the only buffer used, resulting in path being printed that do not belong
to the current thread.
Drop the call since printing the APIC ID is sufficient and thread safe.
Change-Id: I0cbc9cb11da8397ab6c2e8e56414558a8a0db93b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85288
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On 1st and 2nd gen Xeon-SP the VTD PCI device has different PCI IDs,
depending if it's on the CSTACK or PSTACK.
Make sure to handle all VTD device on all stacks the same.
For later SoCs this was already the case since the PCI devices have
the same PCI ID.
Change-Id: I0d726b5ae620282dd4c9036d536e5e51d19a0a0b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Include stddef.h to fix the compiler error when using ipmi_ocp.h:
src/drivers/ipmi/ocp/ipmi_ocp.h:199:44: error: unknown type name 'size_t'
Change-Id: Iccd131295263460a4939e51e12ece87ea22c417c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85317
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a new config to libpayload whose sole purpose it is to
be as different as possible from the defconfig, in order to try to get
the CI to exercise more code paths and thus catch more issues.
Change-Id: Ia6bd7572056b7a02acb686542810e661e015cc69
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
According to the FDT specification the FDT_END token is supposed to be
the last token in the structure block, not a free-floating token
immediately outside of it. That means we're supposed to count it in
struct_size. It seems that the kernel never cared about this, but some
FDT parsing utilities like `fdtgrep` do.
Change-Id: Icdeadbeefcafed00dbabefeed1337c0debc86836
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85462
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Print the current project version in the console and in the generated
file with the pad configuration. This makes support easier, since we
know which version of the utility was used and whether we need to
re-generate the configuration file if an error was made in the latest
changes in the code. The version string includes several parts:
{major}.{minor}-{last commit in the intelp2m directory}-{?dirty}
The major is incremented if a new platform is added, minor - if changes
in functionality are made. Add dirty if the changes were not taken into
account using git.
Use the following command to print the version:
make version
Change-Id: Id2fd0757c003004af976309a44dbbfff0eb517a7
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67321
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- The generated map of long and short macros should correspond to the
reference ones for all pads (INTEL-SUNRISE-PCH/PAD-MAP). The test
suite is based on the generated macros of a real platform.
- generated field macros should correspond to the RO_FIELDS mask
(INTEL-SUNRISE-PCH/MASK);
- macros generated from the zero values bits of the DW registers should
correspond to the reference ones (INTEL-SUNRISE-PCH/EMRTY).
Use the following command in the console to run all the tests in the
project:
make test
Change-Id: I15c7483f120a330849d4bad036427be205b0911c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
- The generated map of long and short macros should correspond to the
reference ones for all pads (INTEL-LEWISBURG-PCH/PAD-MAP). The test
suite is based on the generated macros of a real platform.
- generated field macros should correspond to the RO_FIELDS mask
(INTEL-LEWISBURG-PCH/MASK);
- macros generated from the zero values bits of the DW registers should
correspond to the reference ones (INTEL-LEWISBURG-PCH/EMRTY).
Change-Id: Iec18462be8428c3f37d546332211a730ee589a2d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67133
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
- The generated map of long and short macros should correspond to
the reference ones for all pads (INTEL-APOLLO-PCH/PAD-MAP). The
test suite is based on the generated macros of a real platform.
- generated field macros should correspond to the RO_FIELDS mask
(INTEL-APOLLO-PCH/MASK);
- macros generated from the zero values bits of the DW registers
should correspond to the reference ones (INTEL-APOLLO-PCH/EMRTY).
Change-Id: I1c47edb31d24930068486c74147c5fbc9b18b4b6
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67134
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Generally the base address of FSP output is already aligned so there is
no need to minus 1. The current code loses 1 byte in the lower DRAM
address space.
Change-Id: Ia8147702aad496c431cf10b896d68a826c9e45b1
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85434
Reviewed-by: Jincheng Li <jincheng.li@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
