Address x1 slot enumeration issues for certain add in cards (AICs)
during boot. This change implements proper power sequencing and adds
support for AICs that use PRSNT2# signaling instead of ClkReq#. The
x1 slot power rail (X1_PCIE_SLOT_PWR_EN via GPP_A8) is pull-high by
design, with GPP_A08 PAD defaulting to GPI configuration. This enables
slot power during early boot phases. PERST# (GPP_D19) is logically
ANDed with PLTRST#, ensuring PLTRST# de-assertion occurs only after x1
slot power stabilization, maintaining proper PCIe timing automatically.
For scenarios requiring power-off at boot, the following sequence
ensures compliance with PCIe link training timing requirements:
Step 1 (romstage): ClkReq PAD off; PERST# asserted; power off
Step 2 (ramstage at BS_PRE_DEVICE exit): Power on; ClkReq PAD on (if
used)
Step 3 (ramstage at BS_DEV_INIT_CHIPS entry): PERST# de-asserted
The CBI fw_config SD field has been redefined to accommodate different
AIC types:
- SD_BAYHUB: For AICs supporting ClkReq# signaling
- SD_GENSYS: For AICs using only PRSNT2# signaling
BUG=None
TEST=Boot Fatcat board with AIC cards configured via CBI fw_config SD
field (SD_BAYHUB or SD_GENSYS). Confirm PCIe device enumeration
appears correctly in boot log. For instance:
[SPEW ] do_pci_scan_bridge for PCI: 00:00:1c.0
[DEBUG] PCI: pci_scan_bus for segment group 00 bus ae
[DEBUG] PCI: 00:ae:00.0 [1217/9860] enabled
The device should be seen from lspci command, such as:
ae:00.0 Class 0805: Device 1217:9860 (rev 01)
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I94a7ee2ecd8d3fd83006297ef68f97ff49e47595
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90000
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move Gen4 SSD power enable (GPP_B10) from ramstage GPIO table to
pre-memory configuration to ensure proper delay between power enable
and reset signals. This is required to fix PCIe speed downgrade or
link failure issues seen with some NVMe parts when a non-serial image
is used for boot.
Changes:
- Enable GPP_B10 (GEN4_SSD_PWREN) in pre_mem_gen4_ssd_pwr_pads
- Remove duplicate GPP_B10 configuration from gen4_ssd_pads
- Remove GPP_B10 from ramstage gpio_table
BUG=None
TEST=Boot to OS, check PCIe link speed for SSD.
Change-Id: I969a0d5576b9a229f70a4d01737b7f594876b106
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90523
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select the discrete TBT controller driver, and configure the necessary
GPIOs for the Alpine Ridge TBT controller to be fully functional.
Add ACPI to ensure the TBT controller properly handles S3 sleep and
resume. Update the documentation w/r/t TBT functionality.
TEST=build/boot Lenovo T480, boot Linux, verify all TBT-related PCI
devices populated, lower USB-C port works for USB data and PCIe.
Change-Id: Ie5586fa72ed6819b9d1c37373c21605d39bad7b4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88490
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The HX boards, using PCH-S, use a discrete Thunderbolt device (Intel
Maple Ridge), as opposed to a built-in one like the boards using PCH-P.
Fixes Thunderbolt on RPL-HX boards using the Maple Ridge controller.
Change-Id: I53d18f3ec5a084431e1113782c791bcb42728350
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76584
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evie (Ivi) Ballou <iviballou@gmail.com>
Add a new driver which enables basic TBT support for the Alpine Ridge,
Titan Ridge, and Maple Ridge discrete Thunderbolt controllers.
This driver will initially be used on the Lenovo T480/T480s and
System76 RPL-HX platform boards.
Ref: edk2-platforms KabylakeOpenBoardPkg reference implementation
Ref: Titan Ridge BIOS Implementation Guide v1.4
Ref: Maple Ridge BIOS Implementation Guide v1.6 (#632472)
Change-Id: Ib78ce43740956fa2c93b9ebddb0eeb319dcc0364
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75286
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The mc_ehl8 variant has an RTC (RV3028-C7) at SMBus address 0x52, which
falls within the SPD EEPROM address range (0x50-0x57). By default, FSP
write-protects this range.
Disable write protection for mc_ehl8 to allow RTC configuration.
TEST=Boot system into OS and use i2ctools to read out registers
0x00-0x06 of the RTC to verify that the driver set the correct date
and time.
Change-Id: I0e6426f57d7e316a74102b1e5352ce9d334eac02
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91200
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The RV3028-C7 driver currently uses i2c_dev_read_at() and
i2c_dev_write_at() for block transfers when accessing RTC registers.
These block transfer functions are not universally supported across all
I2C/SMBus controller implementations in coreboot.
Specifically, the Intel i801 SMBus controller does not implement block
read/write operations, causing the RV3028-C7 driver to fail on platforms
using this controller due to missing transfer ops.
Replace block transfers with byte-by-byte operations
i2c_dev_readb_at() and i2c_dev_writeb_at(). These functions are
supported by i801.
TEST=Verified new SMBus functionality on mc_ehl8 (i801 controller).
Verified I2C functionality still works on mc_ehl2.
Used i2ctools from OS to read out registers 0x00-0x06 and confirmed
values match date/time set in coreboot.
Change-Id: I8a40ae14e62e3acf7c3904a8654c1d58fe4eb813
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91199
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the SMN accessor code from SSDT code to DSDT.
This allows compiletime verification of the ACPI code.
Change-Id: I3cddea079f3bfc37eb4e2b2f4496dce6441b289f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91184
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that the ACP device is always present in DSDT move the
MSG0 method and helper functions into DSDT. This allows to clean
the common ACP code and reduces differences in the runtime code
pathes. The newly introduced DSDT is also verified at compile time.
Change-Id: Ifc55278aa66abcb54691017738cc843e3088d8e8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91159
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Windows 11 ACP driver depends on the ACPI _DSD method, thus
add the data based on the UEFI implementation.
TEST=Windows 11 ACP driver reports no issues any more.
Change-Id: I3e193ee0dbf736aab9f7d21927a01992e2f84973
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Move the ACP ACPI device called ACPD from SSDT to DSDT so that a SoC
or a mainboard DSDT can extend the ACP configuration.
Therefore, drop acpi_device_write_pci_dev() in SSDT. Introduce a STAT
variable in ASL, which defaults to 3 (present, enabled, hidden, not ok)
when the device is set to "off" in the devicetree.cb, since the PCI
device is not actual disabled by FSP. When not disabled in devicetree.cb,
STAT will be overriden in SSDT with the actual device status. The STAT
variable is returned by _STA method.
The ACP child devices where seen on Phoenix and KrackenPoint and not
seen on Rembrandt, Cezanne or Mendocino.
Assume older platforms do not have ACP child devices in ACPI.
TEST=Booted on AMD birman_plus (glinda) and verified ACP is working.
TEST=Set ACP device to off and verified it's marked hidden on Windows 11
Device Manager.
Change-Id: I31c3f01f83f27d0121f9e003e60a7f12d49427f6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Eliminates errors in cbmem log:
[ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping
not found
Change-Id: I562e63365599a2dc62526f5789b7c6c79318cb9e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
This board does not have a DMIC, so update the verb table to
reflect that.
Change-Id: Idd38dc016d7d178002f291ac8a0088e5f7b7490d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Commit 91a1276d53 ("soc/intel/alderlake: Implement WA for DDR5 DIMM
modules") was added to allow FSP to perform the SPD read for DDR5
modules since coreboot did not properly support reading SPD from
EEPROM for DDR5. The same code is copied here for Pantherlake.
BUG=None
TEST=Build fatcat and verify there are no errors
Change-Id: Iacd43774c227fae5edc309dc1e163cc5c87160e4
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91202
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch applies commit 0e7cf3d81d ("soc/intel/alderlake: Fix DDR5
channel mapping") to PantherLake.
DDR5 memory modules have two separate 32-bit channels (40-bit on ECC
memory modules), and the SPD info refers to one channel: the primary
bus width is 32 (or 40) bits and the "DIMM size" is halved. On Panther
Lake, there are 2 memory controllers with 4 32-bit channels each for
DDR5. FSP has 16 positions to store SPD data, some of which are only
used with LPDDR4/LPDDR5.
To try to make things less confusing, FSP abstracts the DDR5 channels
so that the configuration works like on DDR4. This is done by copying
each DIMM's SPD data to the other half-channel. Thus, fix the wrapper
parameters for DDR5 accordingly.
BUG=None
TEST=Build fatcat and verify there are no errors
Change-Id: I10226a2e04905040523d95ba8f5bc56f45606fe6
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91201
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This fixes an integer overflow in the calculation of the offset within
the SPD binary that has caused memory detection failures on some
machines (e.g. this resolves https://ticket.coreboot.org/issues/627 ).
In a nutshell, spd_index (uint8_t) receives an assigned multiplication
by 512 (SPD_SIZE_MAX_DDR4) which will always truncate the result.
Change-Id: I048a73c18c9a3d1b20e2a4276e1714e59550eaf5
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91170
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Root complex always resides at 0:0.0 and is always enabled.
Add a static device in DSDT that can be extended later on.
Change-Id: I1d45f7cd732c41343ac154c313a7ca368b0ea2b3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91183
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Lapis project uses a USB camera and does not have
a MIPI camera, therefore the IPU interface is disabled.
BUG=b:475355637
TEST=emerge-fatcat coreboot
Change-Id: I35273251d73a3f885b7dd8750b746dbca06e9564
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91180
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SMBus controller was previously disabled on the Lapis variant.
Enable the SMBus device in the overridetree to allow the system to
communicate with onboard peripherals like the SPD EEPROMs and
thermal sensors.
BUG=none
TEST=Build and boot on Lapis; verify smbus is initialized.
Change-Id: I9d7254b6c2686ec67392294d45b870e3670f2aca
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91196
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select HAVE_CHARGING_DEBUG_ACCESS_PORT for the Quartz variant.
BUG=b:474297115
TEST=Verified that quartz starts charging when the charger is connected
via the servov4.1 to the C0 port.
TEST=Verified that quartz starts charging when the charger is directly
connected to the C0 port.
TEST=Verified that the battery is charging by checking the battery
State of charge after 20-30 mins of charging.
Change-Id: Ie5e0d980780daa0adeee4e6a3e3525eb2616a29f
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
When the system is in a low-power boot state or early charging mode,
it is necessary to enable charging even when a debug access port
is connected. This ensures that developers can charge the
device while using the servov4.1 with the charger.
This patch updates the charging configuration to enable the debug
access sink by writing to the TYPE_C_TYPE_C_DEBUG_ACCESS_SNK_CFG
register.
BUG=b:474297115
TEST=Build Google/quartz
Change-Id: I155b071e678c8bc0ff0d719ac924b5026b21b37a
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91077
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add CONFIG_LP_DEFCONFIG_OVERRIDE_X64 flag to select default 64-bit
config file in payloads/libpayload/configs directory.
This is used in standalone environment. The existing libpayload
deconfig file is for boards with 32-bit format and deconfig_64
file is added for 64-bit without adding specific
board.[board name] file in libpayload.
BUG=none
TEST=Build with this new flag and check that the libpayload and
depthcharge.elf are built in 64-bit format.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Iac07cf9e3c11e49955c69553407be76ef4f8c060
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84107
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
This CL aims to make the code support ready before touchscreen launch.
BUG=b:483588481
TEST=build brox coreboot image
Change-Id: I9f8715311c976e92049ff3058920039c0d38ba3a
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
This CL aims to make the code support ready before touchscreen launch.
BUG=b:483762467
TEST=build nissa coreboot image
Change-Id: I919f92b782905ea9184203804f5ea095e37e9893
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add configuration for the PCIe Root Port connected to the WiFi 7 module.
BUG=b:481186489
TEST=Build successfully for moxoe. Verify WiFi 7 functionality on
moxie.
Change-Id: I8941b587ac35f6c03654de959cc93350b5604b35
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91103
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This is a reland of
commit c4be70f6ff ("commonlib/list: Support circular list").
In some use cases, we want to add items to the linked list and then
iterate over them with the insertion order. With the current API, the
call site needs to either use the inefficient list_append() function to
append items to the end of the list, or manually maintain a "tail"
node pointer.
To support that use case, add an internal helper function _list_init()
to initialize the list as a circular one with a placeholder head node.
_list_init() is automatically called within list_insert_after() and
list_append(). In list_insert_before(), an assertion is added to avoid
an insertion before the head node (which should be invalid). The
implementation ensures that the list is initialized as a circular one
whenever the first element is added. That also allows all call sites to
be auto-upgraded to the "circular list" implementation without any
modification.
Modify list_for_each() to support circular lists, and improve
list_append() efficiency by inserting the new node before the
placeholder head node. Also add a few assertions in the implementation.
Add a new test case to test iterating over an empty list.
Note that '(uintptr_t)ptr + (uintptr_t)offsetof(typeof(*(ptr)), member)'
was used instead of the simpler '&((ptr)->member)' because GCC9+ assumes
that the address can never be NULL. See commit 88991caf00
("include/list.h: Add support for GCC9+") for details. Now, with the
new list_for_each() implementation, that pointer value can never be
NULL.
Change-Id: Idc22887cce71284c9028dce10eeef9cc16669028
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90962
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Update the logo_bottom_margin for all fatcat variants from 100px to
200px. This adjustment ensures the OEM footer logo and associated
splash text are rendered higher on the screen, improving visibility
and alignment with updated UX requirements.
Modified variants:
- fatcat
- felino
- francka
- kinmen
- lapis
- moonstone
- ruby
Change-Id: Ia0f446768f1b0b13c09873176f79ed4418f28aa2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91155
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for dynamic text scaling based on the display resolution
to ensure bootsplash text remains legible on high-density panels.
Key changes:
- Implement get_resolution_scale() to determine a scaling factor (1x,
2x, or 3x) based on the panel's major dimension (HD, QHD, or 4K).
- Update draw_char() to render glyphs as scaled blocks, repeating each
font pixel across a square of the calculated scale factor.
- Apply the scaling factor to all text layout calculations, including
kerning, character advance, and total string dimensions.
- Ensure anti-aliasing (alpha blending) is correctly applied to each
individual pixel within the scaled blocks.
Change-Id: I8b22019ddaa46f1a24f38d565d946bb28a213791
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Transition the bootsplash text renderer from 1-bit monochrome bitmaps
to 8-bit alpha maps to support text smoothing (anti-aliasing).
Key changes:
- Update fonts.h to declare font_table as a 2D uint8_t array containing
alpha intensity values (0-255) for each pixel.
- Update draw_char() to perform alpha blending by mixing the text color
with the existing background pixel using the formula:
Result = (Color * Alpha + BG * (255 - Alpha)) / 255.
- Regenerate the font table data to reflect the new 8-bit format and
updated character widths.
Change-Id: I9d4dde74d86fd552b30523f3b8ff34fb8fdba782
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Update generate_font.py to produce 8-bit alpha maps instead of 1-bit
packed bitmaps. This enables text smoothing (anti-aliasing) during
framebuffer rendering by providing pixel intensity values (0-255).
Key changes:
- Switch PIL image mode from "1" (monochrome) to "L" (8-bit grayscale).
- Change C data type from uint32_t bit-packed rows to uint8_t byte arrays.
- Implement vertical centering logic using font metrics (ascent/descent).
- Add glyph clipping detection and warnings for both width and height.
- Format C output so each source line represents one glyph row.
Change-Id: Iec8a0123456789abcdef0123456789abcdef0123
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91178
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds platform-level support for dynamic splash screen text
rendering on ChromeOS devices. This implementation interfaces with the
ChromeEC to retrieve battery state-of-charge and charging status,
formatting these into human-readable strings during the bootsplash
stage.
TEST=Able to build and boot google/fatcat.
Change-Id: I5dc57d60cd6be0dc9c79668a8b1560d421e4d6cc
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91095
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable rendering of system status messages during the `low-battery`
bootsplash sequence when `FRAMEBUFFER_SPLASH_TEXT` Kconfig is enabled.
This change adds a 32-byte buffer to capture platform-specific text
(such as battery status) and draws it at the footer of the framebuffer
alongside the logo.
TEST=Able to build and boot google/fatcat.
Change-Id: I298804869eb909201a9056b83e4954e223e2b9bb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Introduce FRAMEBUFFER_SPLASH_TEXT to allow rendering status messages
directly into the linear framebuffer. This enables displaying dynamic
information, such as battery levels or system status, during the
bootsplash stage without requiring complex graphics libraries.
Changes:
- Add Kconfig option to toggle framebuffer text support.
- User to call `render_text_to_framebuffer` to display the text message.
- Include render_text.c in ramstage build when
FRAMEBUFFER_SPLASH_TEXT is enabled.
- Create 24x32 font table entry using GoogleSansFlex_24pt-Medium.ttf.
TEST=Able to build google/fatcat.
Change-Id: I6ac25d8d8a9d3d77a9cc2f8c6e0139268b2066b9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91092
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Expose calculate_logo_coordinates() by moving its declaration to
bootsplash.h and removing the static qualifier in render_bmp.c.
This allows other parts of the codebase, such as the upcoming text
rendering logic, to reuse the existing logo positioning math to
calculate destination coordinates based on alignment settings.
Change-Id: I8f8b767b093d6bc2befefdc55fe2effa38b95752
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91154
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update generate_font.py to support user-defined canvas width and height
via command-line arguments. This replaces the hardcoded 16x24 limits.
Key changes:
- Use argparse for --width and --height parameters.
- Ensure glyphs are left-aligned to the MSB (bit 15 or 31) for
scalability.
TEST=Able to create font table upto 32 pixels wide.
```
python generate_font.py <path_to_ttf> --width 24 --height 32 > font_table.c
```
Change-Id: Ifd02a979abf41a2c2b088ae58bb931f9f6421491
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91165
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure lapis to use coreboot (CHIPSET_LOCKDOWN_COREBOOT) to set BIOS
interface lock. Otherwise, FSP code will be responsible for locking the
chipset.
BUG=None
TEST=Able to build and boot lapis
Change-Id: Ia3a13390e4a1862164d820dd1ee220dea682a6a0
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
I would like to stay on track for everything regarding PantherLake,
given I'm working alongside Intel's engineers to support this SoC
properly.
TigerLake is just a formality, there are only two maintainers currently
and not many systems supported. I own the only TGL-H system in the tree
(erying/tgl) and ELDRID (Google/Volteer baseboard) with TGL-UP3.
Change-Id: I4849aa85787528086e247d9aec8be6138523f5a7
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Currently not all fixed MMIO ranges are advertised to the resource
allocator. This is not an issue as long bottom-up allocation is
used and as long as only small PCI BARs are present on the system.
Properly advertise all fixed MMIO ranges decoded by the PCH:
- RCBA
- TXT private
- TXT reserved
- TPM TIS
- LGMR
- HPET
Also remove subtractive decoding from IOAPIC and SPI ROM. Comments
indicate that there's an issue with the OS, but newer platforms also
don't set it to subtractive. No issue was seen with EDK2 payload and
Linux 6.8.8. As a side effect IOAPIC and SPI ROM are now marked as
reserved in e820, which should help payloads not aware of IOAPIC
and SPI ROM to behave more properly.
TEST=Still boots on Lenovo X220. No issues seen in coreboot or Linux.
New e820 reserved ranges:
[DEBUG] 15. 00000000fec00000-00000000fec00fff: RESERVED
[DEBUG] 16. 00000000fed00000-00000000fed00fff: RESERVED
[DEBUG] 18. 00000000fed1c000-00000000fed3ffff: RESERVED
[DEBUG] 19. 00000000fed45000-00000000fed91fff: RESERVED
[DEBUG] 20. 00000000ff000000-00000000ffffffff: RESERVED
Change-Id: I9c251a8c4a4403c5dc0ad535769d8d893dc64a05
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add new LDNs supported by the NCT6796D:
- 0x11: PGPIO, RI PSOUT Wake-Up
- 0x12: LED control
- 0x15: LED control 2
Change-Id: Icef4d32fad5430cbbe8ee4f3719d603361cfea95
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
The -96D is an updated version of the -91D and has additional LDNs.
This initial commit is a clone of the -91D with strings changed;
additional functionality will be added in subsequent commits.
TEST=tested with out-of-tree board Erying SRMJ4
Change-Id: I8f67c999f4076aaca52c93060a6a461dd9bcc62f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91100
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add extra_dump (-e) support for NCT6791D and NCT6796D to dump all HWM
banked registers: global, SYSFAN, CPUFAN, AUXFAN0, PECI calibration,
PECI setup, AUXFAN1–3 (+AUXFAN4 for -96D). Uses index port at base+5
and data port at base+6, per datasheets.
TEST=build/dump SIO registers for out-of-tree board Erying SRMJ4 with
NCT6796D.
Change-Id: I689374826bc1e38efaa3d68013610a8fa2052b1f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91098
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Per the NCT6791D datasheet, global configuration register 0x2d is
reserved, so exclude it from the dump like other reserved registers
(0x12, 0x15-0x19, 0x23, etc).
This was discovered when comparing datasheets for the -91D and -96D;
0x2d is a strapped register for the -96D, but reserved for the -91D.
Change-Id: I7d0372c4592f5532480acc5220ee11d9800d2277
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91097
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Add SMM_TSEG_SIZE for Apollo Lake and Gemini Lake, set to same value as
used by other Intel SoCs. This is required since commit c078552e71
("soc/intel: Replace sa_get_tseg_size() with CONFIG_SMM_TSEG_SIZE")
removed the use of sa_get_tseg_size() without verifying that all SoCs
actually set the Kconfig being used to replace it.
TEST=build google/reef and verify CONFIG_SMM_TSEG_SIZE set in .config.
Change-Id: Iaac2eaddc6ef3ccfa299b8b10103d26d08881370
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Add support to invoke LPASS Initialization. Implement
voting-based enablement for the core HM GDSC and AON CC PLL
instead of direct control.
BUG=b:480195888
Test=1. Create an image.serial.bin and ensure it boots on X1P42100.
2. Verified LP0 BCM vote using serial logs.
Serial Log:
[DEBUG] BCM: Found address 0x00050048 for resource LP0
[INFO ] BCM: Successfully voted for LP0 (addr=0x00050048, val=0x60004001)
3. Verified if the clocks are enabled by taking clock dump. Clock
enablement is verified by dumping the 31st bit of the corresponding
clock’s CBCR register. A value of 0 in bit 31 indicates that the clock
is ON. The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
4. Able to boot X1P42100 w/o any adsp failed to bootup error.
Change-Id: I51ca2b7a5da8b35d0d8dd803000f1db28441c136
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The Birman+ evaluation board allows to test different display
connectors (HDMI, Displayport, ...) by plugin in different "NOVA"
cards. Every NOVA card has a small EEPROM identifying the connector.
Currently the graphics init isn't working with a DisplayPort
monitor connected to the DP NOVA card.
Fix the auto-detection code of the NOVA card. The code was swapping
the endianness of the connector_type which isn't necessary according
to the spec, but it looks like some cards where programmed with
different endianness.
To support both types, little and big endian, accept both for now.
TEST=Can boot into EDK2 with graphics enabled.
Change-Id: I54754967dd4887363043808116495cb36c636baf
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
cbfstool/flashmap/kv_pair.h uses the `__printf` macro. So we need to
include the header file defining `__printf` in the compilation.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I4ce98f59b94d64ef4e0694e0c83f7b83f6feec7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
