Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.
Change-Id: I4e4f5c071f4299876e4ecd9defe7782c85eac3d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91351
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.
Change-Id: I4be1ac4644c461fd64766e27383e479ff518a889
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91350
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.
Change-Id: I009413db0873c42a98cfc8bddb8613c66d496947
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91349
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.
Change-Id: I491f92b334d0e9f98737b94a7232e9361e86743d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91348
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.
Change-Id: I77bfefd0bf173da34675ad64253daae472834bb8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.
Change-Id: Ib480c7dcd99eb5bf16b124584b4e7dbad90d0c84
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.
Change-Id: I8f3a69dfb9fb915c44c9a5486512aa82c2615fab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.
In this case, the callback function already treated the option as if
it were a boolean option, which likely only worked by chance.
Change-Id: I747ecd0b5a33d2773eda409e6578362d694154ee
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91344
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.
In this case, the callback function already treated the option as if
it were a boolean option, which likely only worked by chance.
Change-Id: I7e53c791d48bd5ce5271505c59856bf7ff18e6d0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91343
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.
Change-Id: I3c73f289271eb4bba899bbfe9d3036171cb31d7b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.
The "volume" option has been left as-is because the code reading its
value does not seem to handle it like a boolean.
Change-Id: If183957cff6097187904e0d76c7d3ad997fe365c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91341
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit f530d37da7 ("mb/lenovo/x220: Add PCIe ports in CFR") introduced
several enum options for "Enabled"/"Disabled" settings. These work like
bool options, except that they add extra bloat to the resulting CFR data
structures.
Replace the enum options with bool options. Also rename the macro as it
no longer generates an enum option. While we're at it, properly format
"Wi-Fi" and drop a blank line at the start of a file.
Also, since checkpatch complains about the macro including a trailing
semicolon, drop it from the macro definition and add it at the end of
every use of the macro.
Change-Id: I7889e22d12e01171ed77ae98d29bbd067e45d82b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91340
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
For some reason, there is a blank line at the beginning of these files.
There is no reason to keep this line, so drop it for consistency.
Change-Id: I38092fae7a3f32b34c15d1b4500c4009fca4d5e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Introduce SOC_QUALCOMM_QCLIB_SKIP_MMU_TOGGLE to allow platforms to
maintain the MMU state across the QCLib execution boundary.
Traditionally, coreboot enables the MMU and performs cache maintenance
before disabling it and handing control to QCLib. QCLib then performs
its own initialization: saving MMU registers, performing cache flushes,
and disabling the MMU before returning to coreboot. During the
subsequent entry, QCLib would restore registers and repeat the cycle.
By selecting this Kconfig, we optimize boot time by avoiding these
repeated enable/disable operations. QCLib is permitted to utilize the
MMU context already established by coreboot, bypassing redundant
reinitialization, register restoration, and expensive cache flushes
to the Point of Coherency.
- Legacy platforms continue to toggle the MMU by default.
- Platforms selecting this option bypass mmu_disable() and mmu_enable().
BUG=b:449871690, b:477139887
TEST=Able to reduce boot time by 600ms while booting google/quenbi.
Change-Id: I6b5e199afc27dcb27d74d2753d2ce269ee22f0ac
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add support for THC-SPI touchscreen configuration in the GPIO pad-based
override logic.
The GPP_E17 pin serves dual purposes depending on the hardware
configuration:
- When touchscreen THC-SPI is present: NF3 (THC HID-SPI CS0)
- When fingerprint sensor is present: NF5 (GSPI0 CS0)
The firmware configuration logic now prioritizes touchscreen THC-SPI
over fingerprint sensor configuration, as these are mutually exclusive
hardware configurations.
BUG=None
TEST=Build ocelot and verify correct GPIO configuration based on
fw_config settings for both touchscreen THC-SPI and fingerprint sensor
configurations
Change-Id: I93deb6352cd0f1168ad53819151c705c6ce48b28
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: P, Usha <usha.p@intel.com>
The lapis hardware design does not have a power load switch for
the SSD. Without it, the platform cannot cut off the main power rail
to the device to enter D3cold.
Therefore, remove the RTD3 chip driver and its associated configurations
in the overridetree to align with the hardware capability. The system
will support D3hot instead of D3cold.
BUG=None
TEST=Build and boot to OS on Lapis, verify SSD functions correctly and
power state transitions align with HW design.
Change-Id: I61f15165e1d41c4f347499e2a7200f30d18bcca7
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Lapis requires the addition of a new fingerprint module, and
the fingerprint module needs to be distinguished via UFSC when
updating the fingerprint module fw.
BUG=b:463867670
TEST=./config/payload_utils/generate_ufsc.py ap
Change-Id: I69846aa404adc76c6446de68749f0fe469e570a3
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Drop useless ACPI code and make the codebase look more like the
T430 codebase. IASL doesn't remove empty scope blocks and it
causes binary differences in the produced DSDT.
TEST=TIMELESS build shows that T530 DSDT is now identical to the
T430 DSDT.
Change-Id: Ie65668b98c5ee772a926a265d09ee20ab8d2e15e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move the TPM entry to make the devicetree.cb look like the T530
devicetree.cb. Should not change any functionality, but changes the
TIMELESS build artifact.
Change-Id: Ia49c8fe9781e4d97aaf5ef38d5d76fdfc8c0f0be
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Fill in the speed in MT/s that the DIMM currently runs at and the
speed it could run at.
Change-Id: I936b97bd517f2fcf80ff403171fc89d4a4487761
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90396
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some silicon initialization modules, like OpenSIL report bus width
extension as 16 bits for ECC for DDR5 memories. Handle this case
correctly for DDR5 and LPDDR5 memories by reporting appropriate
bitfield of the SPD width. This field is used later by coreboot to
calculate the bus extension again, which results in 16bit extension
for ECC.
Change-Id: Ia0a9c221a5d047dd7feb212027f5da2399ccb8e1
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
ACPI stores trackpad_state and kbl_brightness as small indices in
CMOS (per cmos.layout and RPTS/RWAK). The ITE init path treated the
CMOS byte as the EC's raw encoded value, so non-default settings
would fall back (e.g. trackpad disabled, kbd backlight brightness).
Treat CMOS-backed values as LUT indices and fix the kbl_brightness
fallback to use an index.
Change-Id: Id8d320c9544c9fa73b234817717c47f1fa169c64
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91301
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bring in ACPI ASL code from sio/nuvoton/common and hook up the
SIO ACPI suspend hook.
TEST=PS/2 keyboard can wake asus/p8z77-m from S3 but not S5, as
expected.
Change-Id: I8d38928adb840d6fcb4703dd9ad69480813156ca
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89746
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Retire the short-lived special setup to share C code between them, in
favour of the common init code provided by CB:82632.
Tested on asus/p8z77-m with SeaBIOS 1.17.0.
Change-Id: I699fc08d9bfc56dad28eb20042884e979785c070
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Currently DSDT keyboard and mouse device declarations generated by
this file use IDs derived from the logical device number, in the
form of KBD# and PS2# where # is the LDN. This is far from the norm
for mainboards with only one super I/O chip, where they are named
PS2K and PS2M, which is also the names used by the much more
simplistic ASL code in drivers/pc/pc80. They also use hard coded
PNP IDs.
This patch adds two preprocessor symbols, SUPERIO_KBC_PS2KID and
SUPERIO_KBC_PS2MID, to allow these device IDs to be changed, most
likely to PS2K and PS2M. If not defined, existing naming logic is
kept.
Their _HIDs are also changed to refer to EISA ID from Kconfig,
like pc80 does. This in theory allows mainboard to change
their PNP IDs if needed. Only Lenovo laptops actually change this
from the Kconfig default, which is also the formerly hardcoded value.
Goal is to allow eliminating pc80 in favour of this when appropriate,
to avoid potential conflicts that may arise from having duplicate PS/2
devices defined.
TEST=With new symbols undefined, generated dsdt.asl did not change.
Generated dsdt.asl checked for correctness manually via temporary
manual edits, with all combinations of preprocessor controls.
Change-Id: I0dcc94c2cb09fee2e22776fd800c3435a9409c84
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
TEST=Processed dsdt.asl for mainboards using this super I/O chip
only contain changes specifically made by CB:89740.
Change-Id: Id8067e6058b650121e7c830a0cb298752a45d62c
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Make this chip use the common Nuvoton ACPI code before mainboards using
this chip begin to come online.
Change-Id: I000ebc92d1c408a865fb803a2e540ca3cca53ee7
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Define the requisite super I/O chip identities and bring in the common
ACPI code.
Change-Id: I2fbd77b0ddc5618a2da844f6e18ce483774c4cf0
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Define the requisite super I/O chip identities and bring in the common
ACPI code.
Change-Id: I1db85c8d0028a1c3e4a5582f3d0e503b71beac70
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
With few exceptions, Nuvoton super I/O chips have the same
configuration registers.
This patch provides a single set of initialization routines to set
up power loss resume, initialize keyboard, and handle switching
PS/2 port role for mainboards with only one PS/2 port.
Power loss resume handling and PS/2 port role switching can be
controlled using nvram or CFR options. Mainboards lacking such
options will need to add them separately.
The common routines support all currently in-tree Nuvoton SIO chips
except nct5104d, nct6687d, npcd378, wpcm450. They will be hooked up
in follow-up patches.
There is also SMM code to disable PS/2 keyboard wakeup before going to
S5, otherwise the system will also power up with any key on the
keyboard, which is most likely undesirable. To use this, mainboards
must set Kconfig SUPERIO_NUVOTON_PNP_BASE, add smm.c to Makefile.mk
and call it from mainboard_smi_sleep().
Update the help text of HAVE_SHARED_PS2_PORT Kconfig with the final
option name used.
TEST=Both power loss resume and PS/2 port role control work on
asus/p8z77-m with entire train of supporting patches applied.
Change-Id: Ibaddcaa2d77c5b06ddfbb6dbaac00df5e72dd4bd
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
INTRUDER# may be asserted continuously on some Star Labs systems.
Disable routing the event to SMI by default to avoid SMI storms when TCO
SMIs are enabled (e.g. via BOOTMEDIA_SMM_BWP).
This allows boards, like starbook_tgl, which assert INTRUDER# constantly
to boot.
TEST=build/boot starbook_tgl with BOOTMEDIA_SMM_BWP selected
Change-Id: I6a2a188a295cc6be3af2043ea902d45c5bb5b95d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Some platforms can have INTRUDER# asserted continuously. If it is routed
to SMI, this can cause an SMI storm and prevent boot.
Introduce SOC_INTEL_COMMON_BLOCK_SMM_TCO_INTRUDER_SMI_ENABLE to control
whether INTRUDER# is routed to SMI, while keeping TCO SMIs available for
other uses (e.g. SPI sync SMIs needed by BOOTMEDIA_SMM_BWP).
TEST=build
Change-Id: I33eb8ce3bee64c95a4d5a6f95a096577d55c742d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91335
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
When an existing LPC window covers an IO range, but is bigger or starts
earlier the current code doesn't recognize it. It will open another
window overlapping an existing one.
Check if an existing LPC IO window covers the current one and allow it
to be bigger than the entry.
TEST=Thinkpad X280 still boots and error messages are gone.
Should fix the following line seen in the coreboot log of the Lenovo
T480 and compatible:
[ERROR] LPC: Cannot open IO window: 1604 size 1
[ERROR] No more IO windows
[ERROR] LPC: Cannot open IO window: 1606 size 1
[ERROR] No more IO windows
[ERROR] LPC: Cannot open IO window: 1610 size 10
[ERROR] No more IO windows
Change-Id: I586066238b801d2abb1122698fb4092ee0b2f6b9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91171
Reviewed-by: Ladislav Ezr <ladislav@ezr.cz>
Reviewed-by: Johann C Rode <jcrode82@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Galtic has two Elan touchpad options, and since both use the same i2c
address, the runtime i2c detection performed during SSDT generation
can't distinquish between them, leading to both devices being added
to the SSDT. This isn't a problem for Linux, but Windows can't
deal with two touchpads being enabled and using the same resources.
To mitigate this, add a new fw_config field which allows selection
between the two touchpad models, as well as a fallback option for
all devices which are not configured. Users who need to can set the
touchpad type in the SSFC using ectool, and then coreboot will
enable only the selected touchpad at boot.
TEST=build/boot google/dedede (galnat) after setting touchpad type
in SSFC. Verify correct touchpad selected via fw_config, only one
touchpad entry present in SSDT, and touchpad functional under both
Linux and Windows 11.
Change-Id: I36797eb5c8f262782380f95ff3c2e38443cf00c0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This reverts commit ee599486ac.
Having the touchpad type selectable via CFR causes more user confusion
than is solves; switch to using SSFC/fw_config in a subsequent patch.
Change-Id: Ie35d1db19dd2f22ea19289f60dbd86cbf1fa137e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90977
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure the Core Display Clock (CDCLK) frequency selection by setting
the 'vga_cd_clk_freq_sel' register to 1 in the moonstone variant
overridetree. This ensures the display engine operates at the required
frequency (442Mhz) for the panel to meet the hardware configuration.
BUG=b:484559627
TEST=Build and boot google/moonstone, verify display initialization.
Change-Id: I4d3d0082f9f221333150bd5b427b3f20e7a2f154
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91236
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure the Core Display Clock (CDCLK) frequency selection by setting
the 'vga_cd_clk_freq_sel' register to CD_CLK_461MHZ in the ptlrvp
baseboard devicetree. This ensures the display engine operates at
the required frequency for the panel to meet the hardware configuration.
BUG=b:458353982
TEST=Build and boot ptlrvp, verify display initialization.
Change-Id: I34abb742ab5d95da4d21ea22da2b1bc7270f1a9c
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Configure the Core Display Clock (CDCLK) frequency selection by setting
the 'vga_cd_clk_freq_sel' register to CD_CLK_461MHZ in the fatcat
baseboard devicetree. This ensures the display engine operates at the
required frequency for the panel to meet the hardware configuration.
BUG=b:458353982
TEST=Build and boot fatcat/lapis, verify display initialization.
Change-Id: If8812bc66149b402adb7b9159f3a28d35903b785
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This change adds support for configuring higher CD Clock frequencies
for VGA SOL initialization during the Pre-Memory phase.
This feature allows BIOS to request specific display core clock
frequencies when VGA support is enabled during MRC training.
The VgaInitControl field in IGPU_PEI_PREMEM_CONFIG has been extended
to include BIT6-7 for CD Clock frequency selection:
* 0: No higher CD Clock required
* 1: 442 MHz
* 2: 461 MHz
BUG=b:458353982
TEST=Build and boot fatcat/lapis, verify display initialization.
Change-Id: I82fae0d21bb83ed26aad73b830ed15fcd626a9ae
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90795
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add/update FP enable/disable based on SKU ID. This is meant
to resolve a UMA issue with devices that had the FPMCU populated on
non-fp devices. Since the FPMCU is present, and the firmware enables
the power GPIO's based on variant, not SKU, the devices were reporting
data on fingerprint errantly. Specify the SKUs which should not have a
FP sensor and default to true to maintain the legacy behavior for
undefined devices and limit risk. Variants which do not have FP SKUs
will be unaffected.
BUG=b:354769653,b:484162286
TEST=Flash on device, test FP.
Disable test SKU, flash on device, test FP.
To test, run `ectool --name=cros_fp version` in the shell
When enabled, the fpmcu fw version should be displayed.
When disabled, an error should be displayed because the fpmcu
is inaccessible.
Change-Id: I6998534e3b9c5909839aceb886ab04a04f394289
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91329
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Verify that a battery is actually present before setting the boot
mode to LB_BOOT_MODE_OFFMODE_CHARGING. This prevents the system
from incorrectly entering a charging state when running on AC power
without a battery connected.
TEST=Build and boot on bluey with and without battery present.
Verify boot mode transitions correctly.
Change-Id: I67098bc06b34c25429daf516f3891c50930209fe
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Allow the mainboard code to disable USB ports based on GPIO straps,
SKU or user configuration. The mainboard code must implement
mb_usb20_port_override() in romstage to disable USB ports. Ports
that are statically disabled in devicetree cannot be enabled
using this method.
Change-Id: I0fd01e12c05d633695a5fb19ff804e9dc588d6ed
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
- Drop USB OC2#, OC3#, OC4#, OC6#
Those are either pulled high or used as GPIO and used by internal
devices only.
- Disable Port 4, 6, 7. They are unused.
- Add comments with devices connected.
TEST=On Lenovo x220 the USB ports P00, P01, P02, P03, P08, P09, P11,
P13 are still working.
Change-Id: I00b0a36a80b812adb9a4ee976dabb528afd36409
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91233
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allow the user to disable PCIe ports that are not required.
Change-Id: Id2d7640255c347c768387408f27e9f5448cbef01
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Automatically use the CFR driver when EDK2 payload and SMMSTORE
are enabled. Selects the UEFI variable option backend by default
when SMMSTORE is enabled.
Change-Id: Ib7cb122dc863d3449c670d1917ebdd2a0a6317d0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add a build time warning in case the DRIVERS_EFI_VARIABLE_STORE is not
selected, but UefiPayload will have a working firmware menu and will
write non-volatile variables into flash.
Without DRIVERS_EFI_VARIABLE_STORE coreboot will be fully functional,
but the settings made in the firmware menu have no effect at all.
Change-Id: Ib8872297d5d3451834f8ccfdaaee32f23727c178
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Without explicit DDR5 support, print_spd_info() was decoding DDR5 DIMMs
with the DDR4 SPD layout, so banks, ranks, rows, columns, and module
size were all displaying incorrect values.
Add DDR5-specific decoding in spd_bin.c using JESD400-5 byte positions.
Define these offsets in ddr5.h and branch in each getter when
dram_type is DDR5 so printed SPD info matches the actual module.
Fix printk reporting DIMM module size to only report "per channel" when
the DIMM actually contains multiple channels.
TEST=build/boot on out-of-tree board Erying SRMJ4 and Starlabs Starbook
MTL. Verify DIMM info printed in cbmem console is correct.
Change-Id: I7f418db3f89c67c2a71b2c327bb511a78faf7300
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91145
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
