As the card reader isn't on a dedicated USB interface for all variants
for the StarLite, default to disable to ensure that an unused USB port
isn't enabled.
Change-Id: I2176fd6556797e468012c98f7e482b9573b5e3f7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The m920q and m720q are the same board, so rename the m920q to reflect
that
Change-Id: Ieef22530207ad4c35ac3cb4255d2ad65e62b65bf
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90374
Reviewed-by: Evie (Ivi) Ballou <iviballou@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Convert the hybrid graphics mux into a generic device and give it an
alias so that the driver can reference it by name.
Change-Id: Icbf6f298cab9e11acc9363daba68f9fbc613e79d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Both models are quite similar, so reuse existing code and reduce
code duplication.
TEST=TIMELESS build shows identical devicetree.cb, DSDT, cmos layout,
bootblock, romstage and postcar stages. ramstage shows minor
differences as static.c is now build before hda_verb.c, resulting
in different location of data symbols. Binary analysis shows that
the data itself didn't change, just the position in the final
binary.
Change-Id: I2e7cf67c9e2542a199b11257e7349a55e0518aac
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Use the same GEN_DEC ranges as on t430. This makes the code look more
similar, but doesn't change the functionality. It changes the TIMELESS
build artifact.
Change-Id: Ibfac61f615fba2b91101125a2187b45af6dadd19
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91283
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make the T430 look like the T530 codebase by reordering includes,
update the ACPI code and update the CMOS defaults file. Should have
not influence on functionality, but changes the TIMELESS build artifacts.
Change-Id: I2c300ecbf44fa950183ee5e05ba1e05cdf5ff00d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The pin widgets for the internal speakers and microphone should not
have the presence detect flag set, as this causes the jack detect
to fail on some distros, leading to headphone output not working.
TEST=build/boot LINK
Change-Id: I798d0cc4a0f4de65ebe51f1dafaeeb12728d2f40
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Update the Creative CA0132 Pin Widget Verb Table from raw hex config
values to AZALIA_PIN_DESC for NIDs 0x0B–0x13, and use
AZALIA_PIN_CFG_NC(0) for N/C pins (0x0C–0x0F).
Mapping generated by hda-decoder utility.
TEST=build/boot LINK
Change-Id: Ia1c9bce2bf0a71aa3a60678828cbc6bc55f7bfc1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add Micron MT62F1G32D2DS-020 WT:D as id 1, and add Micron
MT62F2G32D4DS-020 WT:D as id 0, resulting in the list below:
DRAM Part Name ID to assign
H58G66CK8BX147 0 (0000)
K3KL9L90EM-MGCU 0 (0000)
MT62F2G32D4DS-023 WT:C 0 (0000)
H58G56CK8BX146 1 (0001)
K3KL8L80EM-MGCU 1 (0001)
MT62F1G32D2DS-023 WT:C 1 (0001)
K3KLALA0EM-MGCU 2 (0010)
MT62F1G32D2DS-020 WT:D 1 (0001)
MT62F2G32D4DS-020 WT:D 0 (0000)
BUG=b:488228474
TEST=emerge-fatcat coreboot, rework by EE
flash it and boot normal.
Change-Id: I23ee56fe7e8f2e2ade75eaaf1fa19b91e784030f
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91452
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We found that the lotso project has already used
variant_is_half_populated. If we continue to use the
mb_get_channel_disable_mask API, it will reduce the memory of each DDR
by half. In reality, we are reducing the number of DDR modules (from 4
to 2), so we should remove mb_get_channel_disable_mask to ensure proper
DIMM identification.
BUG=b:468889066
BRANCH=None
TEST=boot to kernel success, and the log shows that the RAM ID is correct.
Change-Id: Ia7fc4610b3257bc20a871080f52f02e089b8531c
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Commit eb504eb49a ("mb/samsung/lumpy: Fix HDA pin configuration
issues") incorrectly used AZALIA_PIN_CFG_NC(0) as a standalone entry
for NID 0x08. Change to AZALIA_PIN_CFG(0, 0x08, AZALIA_PIN_CFG_NC(0))
so the verb for NID 0x08 is emitted correctly.
Change-Id: Iaf23b6e8791a352758189d92ad9c89414fc5a22d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Modify the flash map (fmd) to reduce the Write-Protected RO (WP_RO)
section from 12M to 8M. The recovered 4M of space is reallocated
to a new RW_UNUSED region positioned before RW_LEGACY.
BUG=None
TEST=Build bluey image and verify FMAP table with 'fmap_decode'.
Ensure resulting layout matches the intended offsets.
Change-Id: I6dde5fac5ba3be5fb28f2cd46c5518d87082c067
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Configure the Core Display Clock (CDCLK) frequency selection by setting
the 'vga_cd_clk_freq_sel' register to CD_CLK_461MHZ in the ocelot
baseboard devicetree. This ensures the display engine operates at the
required frequency for the panel to meet the hardware configuration.
TEST=Build and boot ocelot, verify display initialization.
Change-Id: Ic2f8fccc4391febd342f8f140014c5f3e09472c4
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91312
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that we use the WATCHDOG_TOMBSTONE section to store the watchdog
event magic, there is no need to ask EC for the last reset reason. In
fact, with MEDIATEK_WDT_RESET_BY_SW enabled, EC doesn't even record the
watchdog reset reason.
Enable CHROMEOS_USE_EC_WATCHDOG_FLAG only if MEDIATEK_WDT_RESET_BY_SW is
disabled.
BUG=b:481854714
TEST= After triggering WDT timeout, the following log can be observed:
[NOTE ] coreboot-coreboot-unknown.9999.782bb84 Mon Feb 23 06:42:21 UTC 2026 aarch64 bootblock starting (log level: 8)
[DEBUG] ARM64: Exception handlers installed.
[DEBUG] ARM64: Testing exception
[DEBUG] ARM64: Done test exception
[DEBUG] [booker_init] AP hash rule: 0xbe00
[INFO ] mtk_cksys_init = 0x1
[INFO ] WDT: Status = 0x20000
[INFO ] WDT: Last reset was other reset type: 0x00020000
[INFO ] mtk_wdt_swreset() called!
[INFO ] board_reset() called!
And "elogtool list" contained "Hardware watchdog reset".
Change-Id: I44a940d88948897e6727fad5c87f364e3ba9ac61
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91421
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For MT8196p, watchdog external reset is enabled by kernel configuration,
and EC ignores the reset signal AP_PMIC_WDTRST_L. Therefore, enable
MEDIATEK_WDT_RESET_BY_SW to allow triggering the secondary watchdog
reset via software instead of watchdog hardware.
BUG=b:481854714
TEST=cbmem logs preserved on WDT timeout
Change-Id: Ib6b1ddbe28b0cd2aac2043f18dcd15caf4cac37a
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91420
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refactor trigger_critical_battery_shutdown() to use the newly
implemented platform_handle_emergency_low_battery() hook.
This removes duplicate logic from the Bluey mainboard directory and
ensures consistency with the ChromeOS common battery handling code
for visual alerts and ELOG recording.
BUG=none
BRANCH=none
TEST=Build and boot on Bluey; verify emergency shutdown still
triggers red LEDs and logs ELOG events correctly.
Change-Id: I28da29eb3f0033abe524f7ee12d6b823392e9766
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Initialize the ChromeOS EC LEDs during the bootblock phase for the
fatcat mainboard. This ensures the LEDs are powered on early in the boot
process to provide visual feedback to the user.
This covers edge cases where the lightbar was left in an OFF state
by AP firmware and no EC reset occurred to restore defaults.
TEST=Boot moonstome and verify the LEDs turns on during the
bootblock stage.
Change-Id: I24ce78e4a30ea8fce7d7a90e01525c328db7e325
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Initialize and turn on the Chrome EC lightbar during the early romstage
initialization phase. This ensures that the lightbar is active and
ready to provide visual feedback as early as possible in the boot
process.
This covers edge cases where the lightbar was left in an OFF state
by AP firmware and no EC reset occurred to restore defaults.
BUG=b:477531197
TEST=Boot bluey and verify the lightbar turns on during the
early romstage.
Change-Id: I9336acc83d0455c21378ef7cb77939d4d5d54250
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Turn off the lightbar when the system boots into Low-Battery with
Charger or Off-Mode Charging states.
This ensures that the external lightbar does not provide conflicting
visual signals while the built-in display is showing the charging
animation. Additionally, this prevents unnecessary power consumption
from the lightbar in these power-restricted modes.
BUG=b:477531197
TEST=Boot bluey in off-mode charging; verify lightbar is disabled.
Boot bluey normally; verify lightbar functions as expected.
Change-Id: Ice64d700aee82c780f872a3cb18f8a873e9189f5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add Micron MT62F1G32D2DS-031RF memory part to mem_parts_used.txt
and generate corresponding SPD ID entry.
BUG=b:483845259
TEST=Use part_id_gen to generate related settings
Change-Id: I0476c4dcc55204b8fc278d969fa0f09462671b8c
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91172
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Signal integrity measurement on I2C1 bus showed not optimal rise time.
Therefore the clock frequency is reduced from 400kHz to 100kHz to reach
optimal signal integrity also during coreboot runtime.
TEST=Signal integrity measurement during coreboot runtime.
Change-Id: I9721ede7aa645b2ca46f377bbe557f78c36581f6
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91079
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 9702010123.
Fatcat RVP is sometimes unable to boot when non-serial image is flashed.
Reverting this CL until permanent verified fix is landed.
BUG=b:487523987
TEST=Able to boot fatcat to OS from Gen4 SSD slot
Change-Id: I5c61879cfb6e5f54d439284d1f75db5bfceddd1d
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91422
Reviewed-by: <srinivas.kulkarni@intel.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.
Change-Id: I491f92b334d0e9f98737b94a7232e9361e86743d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91348
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.
Change-Id: I77bfefd0bf173da34675ad64253daae472834bb8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.
Change-Id: Ib480c7dcd99eb5bf16b124584b4e7dbad90d0c84
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.
Change-Id: I8f3a69dfb9fb915c44c9a5486512aa82c2615fab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.
In this case, the callback function already treated the option as if
it were a boolean option, which likely only worked by chance.
Change-Id: I747ecd0b5a33d2773eda409e6578362d694154ee
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91344
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit f530d37da7 ("mb/lenovo/x220: Add PCIe ports in CFR") introduced
several enum options for "Enabled"/"Disabled" settings. These work like
bool options, except that they add extra bloat to the resulting CFR data
structures.
Replace the enum options with bool options. Also rename the macro as it
no longer generates an enum option. While we're at it, properly format
"Wi-Fi" and drop a blank line at the start of a file.
Also, since checkpatch complains about the macro including a trailing
semicolon, drop it from the macro definition and add it at the end of
every use of the macro.
Change-Id: I7889e22d12e01171ed77ae98d29bbd067e45d82b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91340
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
For some reason, there is a blank line at the beginning of these files.
There is no reason to keep this line, so drop it for consistency.
Change-Id: I38092fae7a3f32b34c15d1b4500c4009fca4d5e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Add support for THC-SPI touchscreen configuration in the GPIO pad-based
override logic.
The GPP_E17 pin serves dual purposes depending on the hardware
configuration:
- When touchscreen THC-SPI is present: NF3 (THC HID-SPI CS0)
- When fingerprint sensor is present: NF5 (GSPI0 CS0)
The firmware configuration logic now prioritizes touchscreen THC-SPI
over fingerprint sensor configuration, as these are mutually exclusive
hardware configurations.
BUG=None
TEST=Build ocelot and verify correct GPIO configuration based on
fw_config settings for both touchscreen THC-SPI and fingerprint sensor
configurations
Change-Id: I93deb6352cd0f1168ad53819151c705c6ce48b28
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: P, Usha <usha.p@intel.com>
The lapis hardware design does not have a power load switch for
the SSD. Without it, the platform cannot cut off the main power rail
to the device to enter D3cold.
Therefore, remove the RTD3 chip driver and its associated configurations
in the overridetree to align with the hardware capability. The system
will support D3hot instead of D3cold.
BUG=None
TEST=Build and boot to OS on Lapis, verify SSD functions correctly and
power state transitions align with HW design.
Change-Id: I61f15165e1d41c4f347499e2a7200f30d18bcca7
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Lapis requires the addition of a new fingerprint module, and
the fingerprint module needs to be distinguished via UFSC when
updating the fingerprint module fw.
BUG=b:463867670
TEST=./config/payload_utils/generate_ufsc.py ap
Change-Id: I69846aa404adc76c6446de68749f0fe469e570a3
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Drop useless ACPI code and make the codebase look more like the
T430 codebase. IASL doesn't remove empty scope blocks and it
causes binary differences in the produced DSDT.
TEST=TIMELESS build shows that T530 DSDT is now identical to the
T430 DSDT.
Change-Id: Ie65668b98c5ee772a926a265d09ee20ab8d2e15e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move the TPM entry to make the devicetree.cb look like the T530
devicetree.cb. Should not change any functionality, but changes the
TIMELESS build artifact.
Change-Id: Ia49c8fe9781e4d97aaf5ef38d5d76fdfc8c0f0be
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Bring in ACPI ASL code from sio/nuvoton/common and hook up the
SIO ACPI suspend hook.
TEST=PS/2 keyboard can wake asus/p8z77-m from S3 but not S5, as
expected.
Change-Id: I8d38928adb840d6fcb4703dd9ad69480813156ca
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89746
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
INTRUDER# may be asserted continuously on some Star Labs systems.
Disable routing the event to SMI by default to avoid SMI storms when TCO
SMIs are enabled (e.g. via BOOTMEDIA_SMM_BWP).
This allows boards, like starbook_tgl, which assert INTRUDER# constantly
to boot.
TEST=build/boot starbook_tgl with BOOTMEDIA_SMM_BWP selected
Change-Id: I6a2a188a295cc6be3af2043ea902d45c5bb5b95d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Galtic has two Elan touchpad options, and since both use the same i2c
address, the runtime i2c detection performed during SSDT generation
can't distinquish between them, leading to both devices being added
to the SSDT. This isn't a problem for Linux, but Windows can't
deal with two touchpads being enabled and using the same resources.
To mitigate this, add a new fw_config field which allows selection
between the two touchpad models, as well as a fallback option for
all devices which are not configured. Users who need to can set the
touchpad type in the SSFC using ectool, and then coreboot will
enable only the selected touchpad at boot.
TEST=build/boot google/dedede (galnat) after setting touchpad type
in SSFC. Verify correct touchpad selected via fw_config, only one
touchpad entry present in SSDT, and touchpad functional under both
Linux and Windows 11.
Change-Id: I36797eb5c8f262782380f95ff3c2e38443cf00c0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This reverts commit ee599486ac.
Having the touchpad type selectable via CFR causes more user confusion
than is solves; switch to using SSFC/fw_config in a subsequent patch.
Change-Id: Ie35d1db19dd2f22ea19289f60dbd86cbf1fa137e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90977
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure the Core Display Clock (CDCLK) frequency selection by setting
the 'vga_cd_clk_freq_sel' register to 1 in the moonstone variant
overridetree. This ensures the display engine operates at the required
frequency (442Mhz) for the panel to meet the hardware configuration.
BUG=b:484559627
TEST=Build and boot google/moonstone, verify display initialization.
Change-Id: I4d3d0082f9f221333150bd5b427b3f20e7a2f154
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91236
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure the Core Display Clock (CDCLK) frequency selection by setting
the 'vga_cd_clk_freq_sel' register to CD_CLK_461MHZ in the ptlrvp
baseboard devicetree. This ensures the display engine operates at
the required frequency for the panel to meet the hardware configuration.
BUG=b:458353982
TEST=Build and boot ptlrvp, verify display initialization.
Change-Id: I34abb742ab5d95da4d21ea22da2b1bc7270f1a9c
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Configure the Core Display Clock (CDCLK) frequency selection by setting
the 'vga_cd_clk_freq_sel' register to CD_CLK_461MHZ in the fatcat
baseboard devicetree. This ensures the display engine operates at the
required frequency for the panel to meet the hardware configuration.
BUG=b:458353982
TEST=Build and boot fatcat/lapis, verify display initialization.
Change-Id: If8812bc66149b402adb7b9159f3a28d35903b785
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
