mb/siemens/mc_ehl6: Reduce clock rate for I2C1

Signal integrity measurement on I2C1 bus showed not optimal rise time.
Therefore the clock frequency is reduced from 400kHz to 100kHz to reach
optimal signal integrity also during coreboot runtime.

TEST=Signal integrity measurement during coreboot runtime.

Change-Id: I9721ede7aa645b2ca46f377bbe557f78c36581f6
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91079
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb

@@ -111,6 +111,12 @@ chip soc/intel/elkhartlake
 		[PchSerialIoIndexI2C6] = 1,
         }"
 
+	register "common_soc_config" = "{
+		.i2c[1] = {
+			.speed = I2C_SPEED_STANDARD,
+		},
+	}"
+
 	register "SerialIoUartMode" = "{
 		[PchSerialIoIndexUART0] = PchSerialIoPci,
 		[PchSerialIoIndexUART1] = PchSerialIoPci,