As the card reader isn't on a dedicated USB interface for all variants
for the StarLite, default to disable to ensure that an unused USB port
isn't enabled.
Change-Id: I2176fd6556797e468012c98f7e482b9573b5e3f7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Move the SOC_I2C_DEVFN(n) macro definitions that were duplicated in a
separate "for common code" section at the end of multiple platform
pci_devs.h files.
Platforms affected:
- Alder Lake
- Cannon Lake
- Elkhart Lake
- Jasper Lake
- Skylake
- Tiger Lake
Change-Id: Ie3b3e6a25b0dba1beeadad1ab9acf59cafdbcf4a
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Migrate Tiger Lake to use the common PCH client SMI handler
implementation from the Intel common feature code. This change
eliminates platform-specific code by leveraging the shared smihandler.c
driver.
This commit:
- Adds SOC_PMC_DEV macro definition to soc/pci_devs.h
- Selects SOC_INTEL_COMMON_FEATURE_SMIHANDLER Kconfig
- Removes src/soc/intel/tigerlake/smihandler.c
- Updates Makefile to remove smihandler.c compilation
Tiger Lake uses PCH_DEV_PMC as the PMC device identifier.
Change-Id: Ibe06e4d100b2715aeccfe0ff85dc944ab6cd80fc
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91297
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Migrate Panther Lake to use the common PCH client SMI handler
implementation from the Intel common feature code. This change
eliminates platform-specific code by leveraging the shared smihandler.c
driver.
This commit:
- Adds SOC_PMC_DEV macro definition to soc/pci_devs.h
- Selects SOC_INTEL_COMMON_FEATURE_SMIHANDLER Kconfig
- Removes src/soc/intel/pantherlake/smihandler.c
- Updates Makefile to remove smihandler.c compilation
Panther Lake uses PCI_DEV_PMC as the PMC device identifier.
TEST=Build and boot to the OS on a Fatcat device
Change-Id: I32bf4b678e7edda598319086acccc4983edcbe3e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91296
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Migrate Meteor Lake to use the common PCH client SMI handler
implementation from the Intel common feature code. This change
eliminates platform-specific code by leveraging the shared smihandler.c
driver.
This commit:
- Adds SOC_PMC_DEV macro definition to soc/pci_devs.h
- Selects SOC_INTEL_COMMON_FEATURE_SMIHANDLER Kconfig
- Removes src/soc/intel/meteorlake/smihandler.c
- Updates Makefile to remove smihandler.c compilation
Meteor Lake uses PCI_DEV_PMC as the PMC device identifier.
Change-Id: Ia21a6ee0c6fbee6d4ffcfce5fdbe9b3bdf5fcece
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91295
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Migrate Alder Lake to use the common PCH client SMI handler
implementation from the Intel common feature code. This change
eliminates platform-specific code by leveraging the shared smihandler.c
driver.
This commit:
- Adds SOC_PMC_DEV macro definition to soc/pci_devs.h
- Selects SOC_INTEL_COMMON_FEATURE_SMIHANDLER Kconfig
- Removes src/soc/intel/alderlake/smihandler.c
- Updates Makefile to remove smihandler.c compilation
Alder Lake uses PCH_DEV_PMC as the PMC device identifier.
Change-Id: Icbbc7af25e73e952c9b5f811cf0bbe01efe3ae94
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Add a common implementation of SMI handler code for PCH client platforms
to reduce code duplication across Alder Lake, Meteor Lake, Panther Lake,
and Tiger Lake platforms.
This implementation consolidates:
- smihandler_soc_disable_busmaster(): Skip disabling PMC bus master
- southbridge_smi array: Standard SMI handler mappings
The common driver uses a platform-specific macro that must be defined in
each platform's soc/pci_devs.h header:
- SOC_PMC_DEV: PMC PCI device identifier
This change enables consolidation of nearly identical smihandler.c files
across four platforms, reducing duplication by approximately 100+ lines.
Change-Id: I9ecb65b7ea4feafb8acbaf5798bbeaeb80b7c24a
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91293
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Migrate Meteor Lake to use the common PMC utility driver instead
of maintaining platform-specific pmutil.c code.
This change:
- Enables SOC_INTEL_COMMON_FEATURE_PMUTIL in Kconfig
- Removes platform-specific pmutil.c
- Removes pmutil.c from Makefile.mk
The common driver provides all necessary functionality through
the generic config_t interface, eliminating ~290 lines of
duplicated code.
Change-Id: I1c46a517420c8ea7410c4ed7e8e7b761d4399cf9
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Migrate Panther Lake to use the common PMC utility driver instead
of maintaining platform-specific pmutil.c code.
This change:
- Enables SOC_INTEL_COMMON_FEATURE_PMUTIL in Kconfig
- Removes platform-specific pmutil.c
- Removes pmutil.c from Makefile.mk
The common driver provides all necessary functionality through
the generic config_t interface, eliminating ~290 lines of
duplicated code.
TEST=Build and boot to the OS on a Fatcat device
Change-Id: I3ee9630a6b15d7b02776ff633a3cff0766a8915b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91239
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Migrate Alder Lake to use the common PMC utility driver instead
of maintaining platform-specific pmutil.c code.
This change:
- Enables SOC_INTEL_COMMON_FEATURE_PMUTIL in Kconfig
- Removes platform-specific pmutil.c
- Removes pmutil.c from Makefile.mk
The common driver provides all necessary functionality through
the generic config_t interface, eliminating ~290 lines of
duplicated code.
Change-Id: Ieb62ffac95550a0ae8607a3a9ae76e0f6ff0ac35
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
This adds a common PM utility driver for modern Intel platforms that
share consistent PM register layouts.
The driver consolidates power management utility functions that were
previously duplicated across multiple Intel SoC platforms. This
includes functions for:
- SMI/TCO/GPE status bit decoding
- PMC MMIO base address access
- RTC failure detection
- Sleep state management
- Power state structure population
- After-G3 power state configuration
- GPE configuration retrieval using generic config_t
The GPE configuration function (soc_get_gpi_gpe_configs) uses the
generic config_t typedef that each platform defines, allowing complete
code reuse without platform-specific shims.
This common driver is controlled by the Kconfig option
SOC_INTEL_COMMON_FEATURE_PMUTIL and is built for all boot stages.
Change-Id: I45b829b7c18ee66474457df5523069f930806b35
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Replace platform-specific espi.c with the common eSPI/LPC
initialization driver.
Changes:
- Remove src/soc/intel/elkhartlake/espi.c
- Enable SOC_INTEL_COMMON_FEATURE_ESPI in Kconfig
- Update Makefile.mk to remove espi.c from build
The eSPI/LPC initialization was nearly identical across platforms,
differing only in minor header inclusions and ENV_RAMSTAGE wrapper
usage. The common implementation uses the config_t typedef that
each platform defines, providing clean abstraction without
preprocessor conditionals.
Change-Id: I59d9cb1b37bca2c682e2bf87fc3f5b24c34fb920
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Replace platform-specific espi.c with the common eSPI/LPC
initialization driver.
Changes:
- Remove src/soc/intel/jasperlake/espi.c
- Enable SOC_INTEL_COMMON_FEATURE_ESPI in Kconfig
- Update Makefile.mk to remove espi.c from build
The eSPI/LPC initialization was nearly identical across platforms,
differing only in minor header inclusions and ENV_RAMSTAGE wrapper
usage. The common implementation uses the config_t typedef that
each platform defines, providing clean abstraction without
preprocessor conditionals.
Change-Id: Ied29a5f2dabdebe0afedd1d69e4a817d6606a82d
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Replace platform-specific espi.c with the common eSPI/LPC
initialization driver.
Changes:
- Remove src/soc/intel/tigerlake/espi.c
- Enable SOC_INTEL_COMMON_FEATURE_ESPI in Kconfig
- Update Makefile.mk to remove espi.c from build
The eSPI/LPC initialization was nearly identical across platforms,
differing only in minor header inclusions and ENV_RAMSTAGE wrapper
usage. The common implementation uses the config_t typedef that
each platform defines, providing clean abstraction without
preprocessor conditionals.
Change-Id: I65f8af8f5abccff25ec0dead4f7def7ce16d3081
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91220
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace platform-specific espi.c with the common eSPI/LPC
initialization driver.
Changes:
- Remove src/soc/intel/pantherlake/espi.c
- Enable SOC_INTEL_COMMON_FEATURE_ESPI in Kconfig
- Update Makefile.mk to remove espi.c from build
The eSPI/LPC initialization was nearly identical across platforms,
differing only in minor header inclusions and ENV_RAMSTAGE wrapper
usage. The common implementation uses the config_t typedef that
each platform defines, providing clean abstraction without
preprocessor conditionals.
TEST=Build and boot to the OS on a Fatcat device
Change-Id: If5f2de9faa209ff30f986f34b1816ffa6d5fc683
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91219
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace platform-specific espi.c with the common eSPI/LPC
initialization driver.
Changes:
- Remove src/soc/intel/meteorlake/espi.c
- Enable SOC_INTEL_COMMON_FEATURE_ESPI in Kconfig
- Update Makefile.mk to remove espi.c from build
The eSPI/LPC initialization was nearly identical across platforms,
differing only in minor header inclusions and ENV_RAMSTAGE wrapper
usage. The common implementation uses the config_t typedef that
each platform defines, providing clean abstraction without
preprocessor conditionals.
Change-Id: Ifb198964c5eda1fceaec6111cd7fba374bacf1b6
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Replace platform-specific espi.c with the common eSPI/LPC
initialization driver.
Changes:
- Remove src/soc/intel/alderlake/espi.c
- Enable SOC_INTEL_COMMON_FEATURE_ESPI in Kconfig
- Update Makefile.mk to remove espi.c from build
The eSPI/LPC initialization was nearly identical across platforms,
differing only in minor header inclusions and ENV_RAMSTAGE wrapper
usage. The common implementation uses the config_t typedef that
each platform defines, providing clean abstraction without
preprocessor conditionals.
Change-Id: Ifacdd480a9cfd59d9e54faebad82e1cc2db8a8ed
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91217
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This introduces a common implementation for eSPI/LPC initialization
that handles generic IO decode range configuration and standard
interrupt setup. This code is nearly identical across multiple Intel
client platforms.
The implementation includes:
- soc_get_gen_io_dec_range(): Configures generic IO decode ranges
from devicetree (gen1_dec through gen4_dec)
- lpc_soc_init(): Performs legacy ISA/DMA initialization, enables
CLKRUN for power gating, configures Serial IRQ mode, and sets up
the interrupt controllers (IOAPIC, PIRQ, i8259)
Platform-specific configuration is handled through the config_t
typedef that each platform defines via its soc_chip.h header,
eliminating the need for preprocessor conditionals.
The common driver is enabled via the SOC_INTEL_COMMON_FEATURE_ESPI
Kconfig option and works across bootblock, romstage, and ramstage.
Platforms that will use this common implementation:
- Alder Lake
- Meteor Lake
- Panther Lake
- Tiger Lake
- Jasper Lake
- Elkhart Lake
Change-Id: Idbdecff1cef44dae90afb35ff6e2afca011ea5b4
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91216
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Migrate Tiger Lake to use the common SoundWire driver implementation
from the Intel common feature code. This change eliminates platform-
specific code by leveraging the shared soundwire.c driver.
This commit:
- Selects SOC_INTEL_COMMON_FEATURE_SOUNDWIRE Kconfig
- Removes src/soc/intel/tigerlake/soundwire.c
- Updates Makefile to remove soundwire.c compilation
Tiger Lake uses the default values (4 SoundWire master links with ACPI
address 0x40000000).
Change-Id: Ife743d28c8760d9de3f593f7d8caafd7a73efe3a
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Migrate Panther Lake to use the common SoundWire driver implementation
from the Intel common feature code. This change eliminates platform-
specific code by leveraging the shared soundwire.c driver.
This commit:
- Selects SOC_INTEL_COMMON_FEATURE_SOUNDWIRE Kconfig
- Removes src/soc/intel/pantherlake/soundwire.c
- Updates Makefile to remove soundwire.c compilation
Panther Lake uses the default values (4 SoundWire master links with ACPI
address 0x40000000).
TEST=Build and boot to the OS on a Fatcat device
Change-Id: Iaebb27ddc44da536c8e6a6aece1dfee3a4ac7bac
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Migrate Meteor Lake to use the common SoundWire driver implementation
from the Intel common feature code. This change eliminates platform-
specific code by leveraging the shared soundwire.c driver.
This commit:
- Selects SOC_INTEL_COMMON_FEATURE_SOUNDWIRE Kconfig
- Removes src/soc/intel/meteorlake/soundwire.c
- Updates Makefile to remove soundwire.c compilation
Meteor Lake uses the default values (4 SoundWire master links with ACPI
address 0x40000000).
Change-Id: Ib6d412b22cce78caf56ca2d09fcf74e57f54d09c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91278
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Migrate Alder Lake to use the common SoundWire driver implementation
from the Intel common feature code. This change eliminates platform-
specific code by leveraging the shared soundwire.c driver.
This commit:
- Selects SOC_INTEL_COMMON_FEATURE_SOUNDWIRE Kconfig
- Removes src/soc/intel/alderlake/soundwire.c
- Updates Makefile to remove soundwire.c compilation
Alder Lake uses the default values (4 SoundWire master links with ACPI
address 0x40000000).
Change-Id: Idf21d32d0cab9e3c6ca35e2b9f20c42c0455b5bb
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Add a common implementation of soc_fill_soundwire_controller() to reduce
code duplication across multiple Intel SoC platforms. This
implementation consolidates identical SoundWire link configuration code
from Alder Lake, Meteor Lake, Panther Lake, and Tiger Lake platforms.
The common driver uses platform-specific Kconfig options:
- SOC_SOUNDWIRE_ACPI_ADDRESS: ACPI address for the controller
(default 0x40000000)
- SOC_SOUNDWIRE_MASTER_COUNT: Number of SoundWire master links
(default 4)
Platforms can override these defaults in their Kconfig if needed.
This change enables consolidation of nearly identical soundwire.c files
across four platforms, reducing duplication by approximately 210 lines.
Change-Id: I5e188b0b60da91a33cf0325caefbbcabef0ebcba
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91276
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Provide a weak devtree_update() hook and invoke it early in ramstage
at BS_PRE_DEVICE. Mainboards can override devtree_update() to
enable/disable devices at runtime based on CMOS/NVRAM settings.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic84ddb25e1da050543c230ea457042b8a8a3061f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The Linux btintel driver requires DSM function 3 (DSM_SET_RESET_METHOD)
to be supported before it will use the ACPI _PRR/_RST reset path.
Without it, the driver falls back to GPIO or USB reset.
Add set_reset_method callback that returns success. coreboot only
supports WDISABLE2 (GPIO); the _RST method already implements the
toggle. Update the capability buffer (0x03 -> 0x0b) to advertise
function 3 support. Change RDLY default from 105 to 160 ms to match
the Linux driver.
Change-Id: I6a7c9289dcffbbbd769ab3fb4e59765d2fef7598
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91445
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The m920q and m720q are the same board, so rename the m920q to reflect
that
Change-Id: Ieef22530207ad4c35ac3cb4255d2ad65e62b65bf
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90374
Reviewed-by: Evie (Ivi) Ballou <iviballou@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
OSFG is toggled from _PTS/_WAK via MPTS/MWAK and therefore runs for all
supported sleep states. Update the suspend/resume comments to match the
unguarded behavior.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I613efd68ed2770798c2754a1c59f802f47986795
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Commit 1f2408f573 ("console: Fix flushing for slow consoles") fixed a
typo related to some refactoring of the CBMEM fast code path. However,
this also seems to have indirectly broken the SPI flash console, causing
only the console header messages at the beginning of each stage to be
stored.
This is caused by multiple calls to flashconsole_tx_flush() without a
call to flashconsole_tx_byte() in between them. Data is accumulated in a
buffer during calls to flashconsole_tx_byte(), which is then written to
the flash during a flush. If no tx calls occur between flushes, the
second call will try to write data of length 0, which seems to cause
rdev_writeat() to return -1. This causes an early return, since the
return value of rdev_writeat() must match the data length in order for
the rest of the flashconsole_tx_flush to run. The flush function
contains a busy flag to prevent recursive calls to itself, and the early
return prevents it from being reset. Thus, the busy flag remains set for
the remainder of the stage, blocking all future flushes.
The multiple flushes occur because vprintk flushes console drivers after
the string has been sent, but flashconsole_tx_byte() also calls a flush
whenever a newline is encountered. Because of this, flushes are disabled
for the remainder of each stage after the first printk call containing a
newline is stored to the flash console. Although this newline check
could be omitted, flashconsole_tx_byte() also invokes a flush when its
data buffer is full, which shouldn't be avoided.
Prior to the mentioned commit, the incorrect logic happened to prevent
the flush in vprintk, preventing the double flush issue from occurring.
The mentioned commit inverted the logic, allowing the double flush to
occur.
Address this by returning early if len = 0. While we're here,
consolidate the early returns into a single check and change the busy
flag to a bool instead of an int.
TEST=Console messages are not missing in the flashconsole. Tested on the
Lenovo ThinkCentre M900 SFF.
Change-Id: Ic6c2418f04a687610df020df117f7be90b1724b9
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91428
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Convert the hybrid graphics mux into a generic device and give it an
alias so that the driver can reference it by name.
Change-Id: Icbf6f298cab9e11acc9363daba68f9fbc613e79d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Both models are quite similar, so reuse existing code and reduce
code duplication.
TEST=TIMELESS build shows identical devicetree.cb, DSDT, cmos layout,
bootblock, romstage and postcar stages. ramstage shows minor
differences as static.c is now build before hda_verb.c, resulting
in different location of data symbols. Binary analysis shows that
the data itself didn't change, just the position in the final
binary.
Change-Id: I2e7cf67c9e2542a199b11257e7349a55e0518aac
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Use the same GEN_DEC ranges as on t430. This makes the code look more
similar, but doesn't change the functionality. It changes the TIMELESS
build artifact.
Change-Id: Ibfac61f615fba2b91101125a2187b45af6dadd19
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91283
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make the T430 look like the T530 codebase by reordering includes,
update the ACPI code and update the CMOS defaults file. Should have
not influence on functionality, but changes the TIMELESS build artifacts.
Change-Id: I2c300ecbf44fa950183ee5e05ba1e05cdf5ff00d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The pin widgets for the internal speakers and microphone should not
have the presence detect flag set, as this causes the jack detect
to fail on some distros, leading to headphone output not working.
TEST=build/boot LINK
Change-Id: I798d0cc4a0f4de65ebe51f1dafaeeb12728d2f40
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Update the Creative CA0132 Pin Widget Verb Table from raw hex config
values to AZALIA_PIN_DESC for NIDs 0x0B–0x13, and use
AZALIA_PIN_CFG_NC(0) for N/C pins (0x0C–0x0F).
Mapping generated by hda-decoder utility.
TEST=build/boot LINK
Change-Id: Ia1c9bce2bf0a71aa3a60678828cbc6bc55f7bfc1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add Micron MT62F1G32D2DS-020 WT:D as id 1, and add Micron
MT62F2G32D4DS-020 WT:D as id 0, resulting in the list below:
DRAM Part Name ID to assign
H58G66CK8BX147 0 (0000)
K3KL9L90EM-MGCU 0 (0000)
MT62F2G32D4DS-023 WT:C 0 (0000)
H58G56CK8BX146 1 (0001)
K3KL8L80EM-MGCU 1 (0001)
MT62F1G32D2DS-023 WT:C 1 (0001)
K3KLALA0EM-MGCU 2 (0010)
MT62F1G32D2DS-020 WT:D 1 (0001)
MT62F2G32D4DS-020 WT:D 0 (0000)
BUG=b:488228474
TEST=emerge-fatcat coreboot, rework by EE
flash it and boot normal.
Change-Id: I23ee56fe7e8f2e2ade75eaaf1fa19b91e784030f
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91452
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We found that the lotso project has already used
variant_is_half_populated. If we continue to use the
mb_get_channel_disable_mask API, it will reduce the memory of each DDR
by half. In reality, we are reducing the number of DDR modules (from 4
to 2), so we should remove mb_get_channel_disable_mask to ensure proper
DIMM identification.
BUG=b:468889066
BRANCH=None
TEST=boot to kernel success, and the log shows that the RAM ID is correct.
Change-Id: Ia7fc4610b3257bc20a871080f52f02e089b8531c
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Commit eb504eb49a ("mb/samsung/lumpy: Fix HDA pin configuration
issues") incorrectly used AZALIA_PIN_CFG_NC(0) as a standalone entry
for NID 0x08. Change to AZALIA_PIN_CFG(0, 0x08, AZALIA_PIN_CFG_NC(0))
so the verb for NID 0x08 is emitted correctly.
Change-Id: Iaf23b6e8791a352758189d92ad9c89414fc5a22d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reduce BROM settings that are not related to boot to save boot time.
BUG=b:480810041
TEST= 0:1st timestamp reduce from 400ms to 250ms
Change-Id: Ia97a78515d80a141b9b409407f6e41a07261cad9
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Modify the flash map (fmd) to reduce the Write-Protected RO (WP_RO)
section from 12M to 8M. The recovered 4M of space is reallocated
to a new RW_UNUSED region positioned before RW_LEGACY.
BUG=None
TEST=Build bluey image and verify FMAP table with 'fmap_decode'.
Ensure resulting layout matches the intended offsets.
Change-Id: I6dde5fac5ba3be5fb28f2cd46c5518d87082c067
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Implement an algorithm that performs a simple 1D margin training. This
algorithm is generic, i.e. it can be used with multiple margin params.
Use this algorithm to train three margin parameters: RdT, WrT and RdV.
This algorithm also does per-bit calibration, but only for RdT and WrT
since Haswell does not have per-rank per-bit RdV (c.f. `RX_OFFSET_VDQ`
register). Still, implement support in `change_margin()` for all three
types of per-bit margins (WrTBit, RdTBit, RdVBit) for completeness.
Tested on Asrock Z97 Extreme6 with 2 DIMMs per channel (1R + 2R):
- NRI finishes successfully, board still boots to Arch Linux.
- Both fast training as well as S3 suspend/resume still work.
Change-Id: I382cea8e230aee46a0dc66248f1e678d8a9a0090
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89314
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure the Core Display Clock (CDCLK) frequency selection by setting
the 'vga_cd_clk_freq_sel' register to CD_CLK_461MHZ in the ocelot
baseboard devicetree. This ensures the display engine operates at the
required frequency for the panel to meet the hardware configuration.
TEST=Build and boot ocelot, verify display initialization.
Change-Id: Ic2f8fccc4391febd342f8f140014c5f3e09472c4
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91312
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that we use the WATCHDOG_TOMBSTONE section to store the watchdog
event magic, there is no need to ask EC for the last reset reason. In
fact, with MEDIATEK_WDT_RESET_BY_SW enabled, EC doesn't even record the
watchdog reset reason.
Enable CHROMEOS_USE_EC_WATCHDOG_FLAG only if MEDIATEK_WDT_RESET_BY_SW is
disabled.
BUG=b:481854714
TEST= After triggering WDT timeout, the following log can be observed:
[NOTE ] coreboot-coreboot-unknown.9999.782bb84 Mon Feb 23 06:42:21 UTC 2026 aarch64 bootblock starting (log level: 8)
[DEBUG] ARM64: Exception handlers installed.
[DEBUG] ARM64: Testing exception
[DEBUG] ARM64: Done test exception
[DEBUG] [booker_init] AP hash rule: 0xbe00
[INFO ] mtk_cksys_init = 0x1
[INFO ] WDT: Status = 0x20000
[INFO ] WDT: Last reset was other reset type: 0x00020000
[INFO ] mtk_wdt_swreset() called!
[INFO ] board_reset() called!
And "elogtool list" contained "Hardware watchdog reset".
Change-Id: I44a940d88948897e6727fad5c87f364e3ba9ac61
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91421
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For MT8196p, watchdog external reset is enabled by kernel configuration,
and EC ignores the reset signal AP_PMIC_WDTRST_L. Therefore, enable
MEDIATEK_WDT_RESET_BY_SW to allow triggering the secondary watchdog
reset via software instead of watchdog hardware.
BUG=b:481854714
TEST=cbmem logs preserved on WDT timeout
Change-Id: Ib6b1ddbe28b0cd2aac2043f18dcd15caf4cac37a
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91420
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add an I3C driver that allows to use the I3C HW from the OS.
It does:
- Power on/off the I3C HW
- Configures the IOMUX
Add the SoC specific AOAC devices and GPIO pins to reconfigure
the GPIO for I3C HW.
New log messages are seen in coreboot:
[DEBUG] MMIO: fedd2000 disabled
TEST: The I3C driver loads on amd/glinda using Ubuntu 25.04.
Change-Id: Ibca20e2a4f0cb0e6006cfa47fd4addbe27504645
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
