mb/lenovo/t430: Merge into t430 into t530
Both models are quite similar, so reuse existing code and reduce
code duplication.
TEST=TIMELESS build shows identical devicetree.cb, DSDT, cmos layout,
bootblock, romstage and postcar stages. ramstage shows minor
differences as static.c is now build before hda_verb.c, resulting
in different location of data symbols. Binary analysis shows that
the data itself didn't change, just the position in the final
binary.
Change-Id: I2e7cf67c9e2542a199b11257e7349a55e0518aac
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Patrick Rudolph
Matt DeVillier
parent
3a5e4660bb
commit
091ae533b9
28 changed files with 144 additions and 698 deletions
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@ -1,80 +0,0 @@
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## SPDX-License-Identifier: GPL-2.0-only
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if BOARD_LENOVO_THINKPAD_T430
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select AZALIA_USE_LEGACY_VERB_TABLE
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select BOARD_ROMSIZE_KB_12288
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select DRIVERS_LENOVO_HYBRID_GRAPHICS
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select DRIVER_LENOVO_SERIALS
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select DRIVER_LENOVO_SERIALS_EARLY_LOCK
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select DRIVERS_RICOH_RCE822
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select EC_LENOVO_H8
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select EC_LENOVO_PMH7
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select GFX_GMA_PANEL_1_ON_LVDS
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select H8_HAS_BAT_THRESHOLDS_IMPL
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select H8_HAS_BDC_GPIO_DETECTION
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select H8_HAS_WWAN_GPIO_DETECTION
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_CMOS_DEFAULT
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select HAVE_OPTION_TABLE
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select INTEL_GMA_HAVE_VBT
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select INTEL_INT15
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select MAINBOARD_HAS_LIBGFXINIT
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select MAINBOARD_HAS_TPM1
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select MAINBOARD_USES_IFD_GBE_REGION
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select MEMORY_MAPPED_TPM
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select NO_UART_ON_SUPERIO
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select SERIRQ_CONTINUOUS_MODE
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select SOUTHBRIDGE_INTEL_C216
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select SYSTEM_TYPE_LAPTOP
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select USE_NATIVE_RAMINIT
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config VBOOT
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select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
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select GBB_FLAG_DISABLE_FWMP
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select GBB_FLAG_DISABLE_LID_SHUTDOWN
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select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
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select HAS_RECOVERY_MRC_CACHE
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select VBOOT_VBNV_FLASH
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config VBOOT_SLOTS_RW_AB
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default y
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config CBFS_SIZE
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default 0x700000
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config FMDFILE
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default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwab.fmd" if VBOOT
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config MAINBOARD_DIR
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default "lenovo/t430"
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config MAINBOARD_PART_NUMBER
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default "ThinkPad T430"
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config VGA_BIOS_ID
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string
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default "8086,0166"
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config DRAM_RESET_GATE_GPIO
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int
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default 10
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config USBDEBUG_HCD_INDEX
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int
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default 2
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config PS2K_EISAID
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default "PNP0303"
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config PS2M_EISAID
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default "LEN0015"
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config THINKPADEC_HKEY_EISAID
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default "LEN0068"
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endif
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@ -1,4 +0,0 @@
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## SPDX-License-Identifier: GPL-2.0-only
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config BOARD_LENOVO_THINKPAD_T430
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bool "ThinkPad T430"
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@ -1,8 +0,0 @@
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## SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += gpio.c
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romstage-y += gpio.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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bootblock-y += early_init.c
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romstage-y += early_init.c
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@ -1,4 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <ec/lenovo/h8/acpi/ec.asl>
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#include <ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl>
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@ -1,23 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* The _PTS method (Prepare To Sleep) is called before the OS is
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* entering a sleep state. The sleep state number is passed in Arg0
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*/
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Method(_PTS,1)
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{
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\_SB.PCI0.LPCB.EC.MUTE(1)
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\_SB.PCI0.LPCB.EC.USBP(0)
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\_SB.PCI0.LPCB.EC.RADI(0)
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}
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/* The _WAK method is called on system wakeup */
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Method(_WAK,1)
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{
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/* Wake the HKEY to init BT/WWAN */
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\_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0)
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/* Not implemented. */
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Return(Package(){0,0})
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}
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@ -1,3 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <drivers/pc80/pc/ps2_controller.asl>
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@ -1,15 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi_gnvs.h>
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#include <soc/nvs.h>
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void mainboard_fill_gnvs(struct global_nvs *gnvs)
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{
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/* The lid is open by default */
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gnvs->lids = 1;
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/* Temperature at which OS will shutdown */
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gnvs->tcrt = 100;
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/* Temperature at which OS will throttle CPU */
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gnvs->tpsv = 90;
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}
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@ -1,6 +0,0 @@
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Category: laptop
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ROM package: SOIC-8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: n
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Release year: 2012
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@ -1,20 +0,0 @@
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## SPDX-License-Identifier: GPL-2.0-only
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boot_option=Fallback
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debug_level=Debug
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power_on_after_fail=Disable
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nmi=Enable
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volume=0x3
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first_battery=Primary
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bluetooth=Enable
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wwan=Enable
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wlan=Enable
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touchpad=Enable
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sata_mode=AHCI
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fn_ctrl_swap=Disable
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sticky_fn=Disable
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trackpoint=Enable
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backlight=Both
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hybrid_graphics_mode=Integrated Only
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usb_always_on=Disable
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me_state=Normal
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@ -1,108 +0,0 @@
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## SPDX-License-Identifier: GPL-2.0-only
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# -----------------------------------------------------------------
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entries
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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388 4 h 0 reboot_counter
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# -----------------------------------------------------------------
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# coreboot config options: console
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395 4 e 6 debug_level
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#400 8 r 0 reserved for century byte
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# coreboot config options: southbridge
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408 1 e 1 nmi
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409 2 e 7 power_on_after_fail
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# coreboot config options: EC
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411 1 e 8 first_battery
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412 1 e 1 bluetooth
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413 1 e 1 wwan
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414 1 e 1 touchpad
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415 1 e 1 wlan
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416 1 e 1 trackpoint
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417 1 e 1 fn_ctrl_swap
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418 1 e 1 sticky_fn
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419 2 e 13 usb_always_on
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421 1 e 9 sata_mode
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422 2 e 10 backlight
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# coreboot config options: ME
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424 1 e 14 me_state
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425 2 h 0 me_state_prev
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# coreboot config options: northbridge
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432 3 e 11 gfx_uma_size
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435 2 e 12 hybrid_graphics_mode
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440 8 h 0 volume
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# VBOOT
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448 128 r 0 vbnv
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# SandyBridge MRC Scrambler Seed values
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896 32 r 0 mrc_scrambler_seed
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928 32 r 0 mrc_scrambler_seed_s3
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960 16 r 0 mrc_scrambler_seed_chk
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# coreboot config options: check sums
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984 16 h 0 check_sum
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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6 0 Emergency
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6 1 Alert
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6 2 Critical
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6 3 Error
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6 4 Warning
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6 5 Notice
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6 6 Info
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6 7 Debug
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6 8 Spew
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7 0 Disable
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7 1 Enable
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7 2 Keep
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8 0 Secondary
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8 1 Primary
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9 0 AHCI
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9 1 Compatible
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10 0 Both
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10 1 Keyboard only
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10 2 Thinklight only
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10 3 None
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11 0 32M
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11 1 64M
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11 2 96M
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11 3 128M
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11 4 160M
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11 5 192M
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11 6 224M
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12 0 Integrated Only
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12 1 Discrete Only
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12 2 Dual Graphics
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13 0 Disable
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13 1 AC and battery
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13 2 AC only
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14 0 Normal
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14 1 Disabled
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# -----------------------------------------------------------------
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checksums
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checksum 392 447 984
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@ -1,166 +0,0 @@
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chip northbridge/intel/sandybridge
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register "gfx" = "GMA_STATIC_DISPLAYS(1)"
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# Enable DisplayPort Hotplug with 6ms pulse
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register "gpu_dp_d_hotplug" = "0x06"
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# Enable Panel as LVDS and configure power delays
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register "gpu_panel_port_select" = "PANEL_PORT_LVDS"
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register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms
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register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms
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register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms
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register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms
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register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms
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register "gpu_cpu_backlight" = "0x1155"
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register "gpu_pch_backlight" = "0x11551155"
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register "spd_addresses" = "{0x50, 0, 0x51, 0}"
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device domain 0 on
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subsystemid 0x17aa 0x21f3 inherit
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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register "docking_supported" = "true"
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register "gen1_dec" = "0x000c15e1"
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register "gen2_dec" = "0x007c1601"
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register "gen3_dec" = "0x000c06a1"
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register "gpi13_routing" = "2"
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register "gpi1_routing" = "2"
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register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
|
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register "pcie_port_coalesce" = "true"
|
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register "sata_interface_speed_support" = "0x3"
|
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register "sata_port_map" = "0x17"
|
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|
||||
# Do not enable xHCI Port 4 since WWAN USB is EHCI-only
|
||||
register "superspeed_capable_ports" = "0x7"
|
||||
register "xhci_switchable_ports" = "0x7"
|
||||
register "usb_port_config" = "{
|
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{ 1, 1, 0 },
|
||||
{ 1, 1, 1 },
|
||||
{ 1, 2, 3 },
|
||||
{ 1, 1, -1 },
|
||||
{ 1, 1, 2 },
|
||||
{ 1, 0, -1 },
|
||||
{ 0, 0, -1 },
|
||||
{ 1, 2, -1 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 1, 5 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 3, -1 },
|
||||
{ 1, 1, -1 }
|
||||
}"
|
||||
|
||||
# device specific SPI configuration
|
||||
register "spi_uvscc" = "0x2005"
|
||||
register "spi_lvscc" = "0x2005"
|
||||
|
||||
device ref xhci on end # USB 3.0 Controller
|
||||
device ref mei1 on end # Management Engine Interface 1
|
||||
device ref mei2 off end # Management Engine Interface 2
|
||||
device ref me_ide_r off end # Management Engine IDE-R
|
||||
device ref me_kt off end # Management Engine KT
|
||||
device ref gbe on end # Intel Gigabit Ethernet
|
||||
device ref ehci2 on end # USB2 EHCI #2
|
||||
device ref hda on end # High Definition Audio controller
|
||||
device ref pcie_rp1 on # PCIe Port #1
|
||||
chip drivers/ricoh/rce822 # Ricoh cardreader
|
||||
register "disable_mask" = "0x87"
|
||||
register "sdwppol" = "1"
|
||||
device pci 00.0 on end # Ricoh SD card reader
|
||||
end
|
||||
end
|
||||
device ref pcie_rp2 on end # PCIe Port #2
|
||||
device ref pcie_rp3 on # PCIe Port #3
|
||||
smbios_slot_desc "7" "3" "ExpressCard Slot" "8"
|
||||
end
|
||||
device ref pcie_rp4 off end # PCIe Port #4
|
||||
device ref pcie_rp5 off end # PCIe Port #5
|
||||
device ref pcie_rp6 off end # PCIe Port #6
|
||||
device ref pcie_rp7 off end # PCIe Port #7
|
||||
device ref pcie_rp8 off end # PCIe Port #8
|
||||
device ref ehci1 on end # USB2 EHCI #1
|
||||
device ref pci_bridge off end # PCI bridge
|
||||
device ref lpc on # LPC bridge PCI-LPC bridge
|
||||
chip ec/lenovo/pmh7
|
||||
register "backlight_enable" = "true"
|
||||
register "dock_event_enable" = "true"
|
||||
device pnp ff.1 on end # dummy
|
||||
end
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
chip ec/lenovo/h8
|
||||
device pnp ff.2 on # dummy
|
||||
io 0x60 = 0x62
|
||||
io 0x62 = 0x66
|
||||
io 0x64 = 0x1600
|
||||
io 0x66 = 0x1604
|
||||
end
|
||||
register "config0" = "0xa7"
|
||||
register "config1" = "0x01"
|
||||
register "config2" = "0xa0"
|
||||
register "config3" = "0xe2"
|
||||
|
||||
register "has_keyboard_backlight" = "0"
|
||||
|
||||
register "beepmask0" = "0x02"
|
||||
register "beepmask1" = "0x86"
|
||||
register "has_power_management_beeps" = "1"
|
||||
register "event2_enable" = "0xff"
|
||||
register "event3_enable" = "0xff"
|
||||
register "event4_enable" = "0xf0"
|
||||
register "event5_enable" = "0x3c"
|
||||
register "event6_enable" = "0x00"
|
||||
register "event7_enable" = "0xa1"
|
||||
register "event8_enable" = "0x7b"
|
||||
register "event9_enable" = "0xff"
|
||||
register "eventa_enable" = "0x00"
|
||||
register "eventb_enable" = "0x00"
|
||||
register "eventc_enable" = "0xff"
|
||||
register "eventd_enable" = "0xff"
|
||||
register "evente_enable" = "0x0d"
|
||||
|
||||
register "bdc_gpio_num" = "54"
|
||||
register "bdc_gpio_lvl" = "0"
|
||||
|
||||
register "wwan_gpio_num" = "70"
|
||||
register "wwan_gpio_lvl" = "0"
|
||||
end
|
||||
chip drivers/lenovo/hybrid_graphics
|
||||
device pnp ff.f on end # dummy
|
||||
|
||||
register "detect_gpio" = "21"
|
||||
|
||||
register "has_panel_hybrid_gpio" = "true"
|
||||
register "panel_hybrid_gpio" = "52"
|
||||
register "panel_integrated_lvl" = "true"
|
||||
|
||||
register "has_backlight_gpio" = "false"
|
||||
register "has_dgpu_power_gpio" = "false"
|
||||
|
||||
register "has_thinker1" = "true"
|
||||
end
|
||||
end
|
||||
device ref sata1 on end # SATA Controller 1
|
||||
device ref smbus on # SMBus
|
||||
chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip
|
||||
device i2c 54 on end
|
||||
device i2c 55 on end
|
||||
device i2c 56 on end
|
||||
device i2c 57 on end
|
||||
device i2c 5c on end
|
||||
device i2c 5d on end
|
||||
device i2c 5e on end
|
||||
device i2c 5f on end
|
||||
end
|
||||
end
|
||||
device ref sata2 off end # SATA Controller 2
|
||||
device ref thermal off end # Thermal
|
||||
end
|
||||
device ref host_bridge on end # Host bridge Host bridge
|
||||
device ref peg10 on end # PCIe Bridge for discrete graphics
|
||||
device ref igd on end # Internal graphics VGA controller
|
||||
device ref dev4 off end # Signal processing controller
|
||||
end
|
||||
end
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#define THINKPAD_EC_GPE 17
|
||||
#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
|
||||
#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
|
||||
|
||||
#include <acpi/acpi.h>
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
ACPI_DSDT_REV_2,
|
||||
OEM_ID,
|
||||
ACPI_TABLE_CREATOR,
|
||||
0x20110725 // OEM revision
|
||||
)
|
||||
{
|
||||
#include <acpi/dsdt_top.asl>
|
||||
#include <southbridge/intel/common/acpi/platform.asl>
|
||||
|
||||
#include "acpi/platform.asl"
|
||||
|
||||
// global NVS and variables
|
||||
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
|
||||
|
||||
#include <cpu/intel/common/acpi/cpu.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
Device (PCI0)
|
||||
{
|
||||
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
|
||||
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
|
||||
|
||||
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
|
||||
}
|
||||
}
|
||||
|
||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
#include <ec/lenovo/h8/acpi/thinklight.asl>
|
||||
}
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/pci_ops.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <ec/lenovo/pmh7/pmh7.h>
|
||||
#include <drivers/i2c/at24rf08c/lenovo.h>
|
||||
#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
|
||||
#include <northbridge/intel/sandybridge/sandybridge.h>
|
||||
|
||||
static void hybrid_graphics_init(void)
|
||||
{
|
||||
bool peg, igd;
|
||||
u32 reg32;
|
||||
|
||||
early_hybrid_graphics(&igd, &peg);
|
||||
|
||||
if (peg && igd)
|
||||
return;
|
||||
|
||||
/* Hide disabled devices */
|
||||
reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN);
|
||||
reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD);
|
||||
|
||||
if (peg)
|
||||
reg32 |= DEVEN_PEG10;
|
||||
|
||||
if (igd)
|
||||
reg32 |= DEVEN_IGD;
|
||||
else
|
||||
/* Disable IGD VGA decode, no GTT or GFX stolen */
|
||||
pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2);
|
||||
|
||||
pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
|
||||
}
|
||||
|
||||
void mainboard_early_init(bool s3resume)
|
||||
{
|
||||
hybrid_graphics_init();
|
||||
lenovo_mainboard_eeprom_lock();
|
||||
}
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
-- SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
with HW.GFX.GMA;
|
||||
with HW.GFX.GMA.Display_Probing;
|
||||
|
||||
use HW.GFX.GMA;
|
||||
use HW.GFX.GMA.Display_Probing;
|
||||
|
||||
private package GMA.Mainboard is
|
||||
|
||||
ports : constant Port_List :=
|
||||
(DP1,
|
||||
DP2,
|
||||
DP3,
|
||||
HDMI1,
|
||||
HDMI2,
|
||||
HDMI3,
|
||||
Analog,
|
||||
LVDS,
|
||||
others => Disabled);
|
||||
|
||||
end GMA.Mainboard;
|
||||
|
|
@ -1,15 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/device.h>
|
||||
#include <drivers/intel/gma/int15.h>
|
||||
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
|
||||
GMA_INT15_PANEL_FIT_DEFAULT,
|
||||
GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
|
@ -1,68 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <ec/acpi/ec.h>
|
||||
#include <ec/lenovo/h8/h8.h>
|
||||
#include <southbridge/intel/common/pmutil.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
|
||||
#define GPE_EC_SCI 1
|
||||
#define GPE_EC_WAKE 13
|
||||
|
||||
static void mainboard_smi_handle_ec_sci(void)
|
||||
{
|
||||
u8 status = inb(EC_SC);
|
||||
u8 event;
|
||||
|
||||
if (!(status & EC_SCI_EVT))
|
||||
return;
|
||||
|
||||
event = ec_query();
|
||||
printk(BIOS_DEBUG, "EC event %#02x\n", event);
|
||||
}
|
||||
|
||||
void mainboard_smi_gpi(u32 gpi_sts)
|
||||
{
|
||||
if (gpi_sts & (1 << GPE_EC_SCI))
|
||||
mainboard_smi_handle_ec_sci();
|
||||
}
|
||||
|
||||
int mainboard_smi_apmc(u8 data)
|
||||
{
|
||||
switch (data) {
|
||||
case APM_CNT_ACPI_ENABLE:
|
||||
/* use 0x1600/0x1604 to prevent races with userspace */
|
||||
ec_set_ports(0x1604, 0x1600);
|
||||
/* route EC_SCI to SCI */
|
||||
gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI);
|
||||
/* discard all events, and enable attention */
|
||||
ec_write(0x80, 0x01);
|
||||
break;
|
||||
case APM_CNT_ACPI_DISABLE:
|
||||
/* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
|
||||
provide a EC query function */
|
||||
ec_set_ports(0x66, 0x62);
|
||||
/* route EC_SCI to SMI */
|
||||
gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI);
|
||||
/* discard all events, and enable attention */
|
||||
ec_write(0x80, 0x01);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void mainboard_smi_sleep(u8 slp_typ)
|
||||
{
|
||||
if (slp_typ == 3) {
|
||||
u8 ec_wake = ec_read(0x32);
|
||||
/* If EC wake events are enabled, enable wake on EC WAKE GPE. */
|
||||
if (ec_wake & 0x14) {
|
||||
/* Redirect EC WAKE GPE to SCI. */
|
||||
gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,21 +0,0 @@
|
|||
FLASH 0xc00000 {
|
||||
SI_ALL 0x20000 {
|
||||
SI_DESC 0x1000
|
||||
SI_GBE 0x2000
|
||||
SI_ME
|
||||
}
|
||||
SI_BIOS 0xbe0000 {
|
||||
UNIFIED_MRC_CACHE 0x20000 {
|
||||
RECOVERY_MRC_CACHE 0x10000
|
||||
RW_MRC_CACHE 0x10000
|
||||
}
|
||||
|
||||
WP_RO {
|
||||
FMAP 0x800
|
||||
RO_FRID 0x40
|
||||
RO_PADDING 0x7c0
|
||||
GBB 0x1e000
|
||||
COREBOOT(CBFS)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,21 +0,0 @@
|
|||
FLASH 0xc00000 {
|
||||
SI_ALL 0x500000 {
|
||||
SI_DESC 0x1000
|
||||
SI_GBE 0x2000
|
||||
SI_ME
|
||||
}
|
||||
SI_BIOS 0x700000 {
|
||||
UNIFIED_MRC_CACHE 0x20000 {
|
||||
RECOVERY_MRC_CACHE 0x10000
|
||||
RW_MRC_CACHE 0x10000
|
||||
}
|
||||
|
||||
WP_RO {
|
||||
FMAP 0x800
|
||||
RO_FRID 0x40
|
||||
RO_PADDING 0x7c0
|
||||
GBB 0x1e000
|
||||
COREBOOT(CBFS)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,35 +0,0 @@
|
|||
FLASH 0xc00000 {
|
||||
SI_ALL@0x0 0x500000 {
|
||||
SI_DESC@0x0 0x1000
|
||||
SI_GBE@0x1000 0x2000
|
||||
SI_ME
|
||||
}
|
||||
SI_BIOS@0x500000 0x700000 {
|
||||
RW_SECTION_A 0x280000 {
|
||||
VBLOCK_A 0x10000
|
||||
FW_MAIN_A(CBFS)
|
||||
RW_FWID_A 0x40
|
||||
}
|
||||
RW_SECTION_B 0x280000 {
|
||||
VBLOCK_B 0x10000
|
||||
FW_MAIN_B(CBFS)
|
||||
RW_FWID_B 0x40
|
||||
}
|
||||
UNIFIED_MRC_CACHE@0x500000 0x20000 {
|
||||
RECOVERY_MRC_CACHE@0x0 0x10000
|
||||
RW_MRC_CACHE@0x10000 0x10000
|
||||
}
|
||||
RW_VPD(PRESERVE) 0x1000
|
||||
SMMSTORE(PRESERVE)@0x521000 0x40000
|
||||
RW_NVRAM(PRESERVE)@0x561000 0x2000
|
||||
|
||||
WP_RO {
|
||||
FMAP 0x800
|
||||
RO_FRID 0x40
|
||||
RO_PADDING 0x7c0
|
||||
RO_VPD(PRESERVE) 0x1000
|
||||
GBB 0x1e000
|
||||
COREBOOT(CBFS)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -38,6 +38,10 @@ config BOARD_LENOVO_W530
|
|||
select BOARD_LENOVO_BASEBOARD_T530
|
||||
select DRIVERS_RICOH_RCE822
|
||||
|
||||
config BOARD_LENOVO_T430
|
||||
select BOARD_LENOVO_BASEBOARD_T530
|
||||
select DRIVERS_RICOH_RCE822
|
||||
|
||||
if BOARD_LENOVO_BASEBOARD_T530
|
||||
|
||||
config VBOOT
|
||||
|
|
@ -60,6 +64,7 @@ config FMDFILE
|
|||
config VARIANT_DIR
|
||||
default "t530" if BOARD_LENOVO_T530
|
||||
default "w530" if BOARD_LENOVO_W530
|
||||
default "t430" if BOARD_LENOVO_T430
|
||||
|
||||
config MAINBOARD_DIR
|
||||
default "lenovo/t530"
|
||||
|
|
@ -70,6 +75,7 @@ config OVERRIDE_DEVICETREE
|
|||
config MAINBOARD_PART_NUMBER
|
||||
default "ThinkPad T530" if BOARD_LENOVO_T530
|
||||
default "ThinkPad W530" if BOARD_LENOVO_W530
|
||||
default "ThinkPad T430" if BOARD_LENOVO_T430
|
||||
|
||||
config USBDEBUG_HCD_INDEX
|
||||
int
|
||||
|
|
@ -84,6 +90,7 @@ config VGA_BIOS_ID
|
|||
default "8086,0166"
|
||||
|
||||
config PS2K_EISAID
|
||||
default "PNP0303" if BOARD_LENOVO_T430
|
||||
default "LEN0071"
|
||||
|
||||
config PS2M_EISAID
|
||||
|
|
|
|||
|
|
@ -5,3 +5,6 @@ config BOARD_LENOVO_T530
|
|||
|
||||
config BOARD_LENOVO_W530
|
||||
bool "ThinkPad W530"
|
||||
|
||||
config BOARD_LENOVO_T430
|
||||
bool "ThinkPad T430"
|
||||
|
|
|
|||
|
|
@ -5,3 +5,4 @@ romstage-y += variants/$(VARIANT_DIR)/gpio.c
|
|||
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
|
||||
bootblock-y += early_init.c
|
||||
romstage-y += early_init.c
|
||||
ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
|
||||
|
|
|
|||
58
src/mainboard/lenovo/t530/variants/t430/overridetree.cb
Normal file
58
src/mainboard/lenovo/t530/variants/t430/overridetree.cb
Normal file
|
|
@ -0,0 +1,58 @@
|
|||
chip northbridge/intel/sandybridge
|
||||
register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms
|
||||
register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms
|
||||
|
||||
register "spd_addresses" = "{0x50, 0, 0x51, 0}"
|
||||
device domain 0 on
|
||||
subsystemid 0x17aa 0x21f3 inherit
|
||||
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
|
||||
register "sata_interface_speed_support" = "0x3"
|
||||
register "sata_port_map" = "0x17"
|
||||
|
||||
# Do not enable xHCI Port 4 since WWAN USB is EHCI-only
|
||||
register "superspeed_capable_ports" = "0x7"
|
||||
register "xhci_switchable_ports" = "0x7"
|
||||
register "usb_port_config" = "{
|
||||
{ 1, 1, 0 },
|
||||
{ 1, 1, 1 },
|
||||
{ 1, 2, 3 },
|
||||
{ 1, 1, -1 },
|
||||
{ 1, 1, 2 },
|
||||
{ 1, 0, -1 },
|
||||
{ 0, 0, -1 },
|
||||
{ 1, 2, -1 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 1, 5 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 3, -1 },
|
||||
{ 1, 1, -1 }
|
||||
}"
|
||||
|
||||
device ref pcie_rp1 on # PCIe Port #1
|
||||
chip drivers/ricoh/rce822 # Ricoh cardreader
|
||||
register "disable_mask" = "0x87"
|
||||
register "sdwppol" = "1"
|
||||
device pci 00.0 on end # Ricoh SD card reader
|
||||
end
|
||||
end
|
||||
device ref lpc on
|
||||
chip ec/lenovo/h8
|
||||
device pnp ff.2 on end # dummy
|
||||
register "wwan_gpio_num" = "70"
|
||||
register "wwan_gpio_lvl" = "0"
|
||||
register "config1" = "0x01"
|
||||
register "config3" = "0xe2"
|
||||
register "has_keyboard_backlight" = "0"
|
||||
register "beepmask0" = "0x02"
|
||||
register "has_power_management_beeps" = "1"
|
||||
register "event4_enable" = "0xf0"
|
||||
register "event5_enable" = "0x3c"
|
||||
register "event7_enable" = "0xa1"
|
||||
register "eventa_enable" = "0x00"
|
||||
end
|
||||
end
|
||||
device ref thermal off end # Thermal
|
||||
end
|
||||
end
|
||||
end
|
||||
75
src/mainboard/lenovo/t530/variants/w530/hda_verb.c
Normal file
75
src/mainboard/lenovo/t530/variants/w530/hda_verb.c
Normal file
|
|
@ -0,0 +1,75 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* Bits 31:28 - Codec Address */
|
||||
/* Bits 27:20 - NID */
|
||||
/* Bits 19:8 - Verb ID */
|
||||
/* Bits 7:0 - Payload */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269VC */
|
||||
0x17aa21fa, /* Subsystem ID */
|
||||
18, /* Number of 4 dword sets */
|
||||
AZALIA_SUBVENDOR(0, 0x17aa21fa),
|
||||
|
||||
/* Ext. Microphone Connector: External,Right; MicIn,3.5mm; Black,JD; DA,Seq */
|
||||
AZALIA_PIN_CFG(0, 0x0a, 0x04a11020),
|
||||
|
||||
/* Headphones Connector: External,Right; HP,3.5mm; Black,JD; DA,Seq */
|
||||
AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
|
||||
|
||||
/* Not connected: N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq */
|
||||
AZALIA_PIN_CFG(0, 0x0c, 0x40f000f0),
|
||||
|
||||
/* Internal Speakers Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq */
|
||||
AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
|
||||
|
||||
/* Not connected */
|
||||
AZALIA_PIN_CFG(0, 0x0f, 0x40f000f0),
|
||||
|
||||
/* Internal Microphone: Fixed,Int,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq */
|
||||
AZALIA_PIN_CFG(0, 0x11, 0xd5a30140),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60140),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x03211020),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x03a11830),
|
||||
AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)),
|
||||
|
||||
0x01970804,
|
||||
0x01870803,
|
||||
0x01470740,
|
||||
0x00970600,
|
||||
|
||||
AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40138205),
|
||||
AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
|
||||
|
||||
/* Misc entries */
|
||||
0x00370600,
|
||||
0x00270600,
|
||||
0x00b707C0, /* Enable PortB as Output with HP amp */
|
||||
0x00d70740, /* Enable PortD as Output */
|
||||
0x0017a200, /* Disable ClkEn of PortSenseTst */
|
||||
0x0017c621, /* Slave Port - Port A used as microphone input for
|
||||
combo Jack
|
||||
Master Port - Port B used for Jack Presence Detect
|
||||
Enable Combo Jack Detection */
|
||||
0x0017a208, /* Enable ClkEn of PortSenseTst */
|
||||
0x00170500, /* Set power state to D0 */
|
||||
|
||||
/* --- Codec #3 --- */
|
||||
0x80862806, /* Codec Vendor / Device ID: Intel PantherPoint HDMI */
|
||||
0x80860101, /* Subsystem ID */
|
||||
4, /* Number of 4 dword sets */
|
||||
AZALIA_SUBVENDOR(3, 0x80860101),
|
||||
AZALIA_PIN_CFG(3, 0x05, 0x18560010),
|
||||
AZALIA_PIN_CFG(3, 0x06, 0x18560020),
|
||||
AZALIA_PIN_CFG(3, 0x07, 0x18560030),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {
|
||||
0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */
|
||||
};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
Loading…
Add table
Add a link
Reference in a new issue