- C 93.8%
- ASL 2.2%
- Makefile 1.1%
- C++ 0.5%
- Pawn 0.5%
- Other 1.8%
Carve out 256K from the RW_UNUSED region to create a new RW_CDT
section at the end of the flash. The RW_UNUSED region is reduced
from 4096K (4M) to 3840K to maintain the existing flash offset
for the start of the unused block.
The RW_CDT region will be used to store Configuration Data Tables,
allowing for platform-specific configuration binary blobs to be
stored and updated in the RW section of the flash.
BUG=b:483194720
TEST=Build bluey and verify the FMAP layout using 'dump_fmap'.
Ensure RW_CDT exists at the expected offset.
dump_fmap -h ../../out/build/bluey/firmware/image-bluey.serial.bin
RW_CDT 01fc0000 02000000 00040000
RW_UNUSED 01c00000 01fc0000 003c0000
RW_LEGACY 0192e000 01c00000 002d2000
RW_SECTION_B 010ae000 0192e000 00880000
RW_FWID_B 0192df00 0192e000 00000100
FW_MAIN_B 010b0000 0192df00 0087df00
VBLOCK_B 010ae000 010b0000 00002000
RW_SECTION_A 0082e000 010ae000 00880000
RW_FWID_A 010adf00 010ae000 00000100
FW_MAIN_A 00830000 010adf00 0087df00
VBLOCK_A 0082e000 00830000 00002000
RW_MISC 00800000 0082e000 0002e000
RW_NVRAM 0082a000 0082e000 00004000
RW_VPD 00822000 0082a000 00008000
RW_SHARED 00821000 00822000 00001000
SHARED_DATA 00821000 00822000 00001000
RW_ELOG 00820000 00821000 00001000
UNIFIED_MRC_CACHE 00800000 00820000 00020000
RW_MRC_CACHE 00810000 00820000 00010000
RECOVERY_MRC_CACHE 00800000 00810000 00010000
WP_RO 00000000 00800000 00800000
RO_VPD 007fc000 00800000 00004000
RO_GSCVD 007fa000 007fc000 00002000
RO_SECTION 00000000 007fa000 007fa000
RO_FRID 007f9f00 007fa000 00000100
GBB 007f7000 007f9f00 00002f00
COREBOOT 00081000 007f7000 00776000
FMAP 00080000 00081000 00001000
BOOTBLOCK 00000000 00080000 00080000
Change-Id: I7d305647731862e61871e781ad7bfb7cd430b699
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
||
|---|---|---|
| 3rdparty | ||
| configs | ||
| Documentation | ||
| LICENSES | ||
| payloads | ||
| spd | ||
| src | ||
| tests | ||
| util | ||
| .checkpatch.conf | ||
| .clang-format | ||
| .editorconfig | ||
| .gitignore | ||
| .gitmodules | ||
| .gitreview | ||
| .mailmap | ||
| AUTHORS | ||
| COPYING | ||
| gnat.adc | ||
| MAINTAINERS | ||
| Makefile | ||
| Makefile.mk | ||
| README.md | ||
| toolchain.mk | ||
coreboot README
coreboot is a Free Software project aimed at replacing the proprietary firmware (BIOS/UEFI) found in most computers. coreboot performs the required hardware initialization to configure the system, then passes control to a different executable, referred to in coreboot as the payload. Most often, the primary function of the payload is to boot the operating system (OS).
With the separation of hardware initialization and later boot logic, coreboot is perfect for a wide variety of situations. It can be used for specialized applications that run directly in the firmware, running operating systems from flash, loading custom bootloaders, or implementing firmware standards, like PC BIOS services or UEFI. This flexibility allows coreboot systems to include only the features necessary in the target application, reducing the amount of code and flash space required.
Source code
All source code for coreboot is stored in git. It is downloaded with the command:
git clone https://review.coreboot.org/coreboot.git.
Code reviews are done in the project's Gerrit instance.
The code may be browsed via coreboot's Gitiles instance.
The coreboot project also maintains a mirror of the project on github. This is read-only, as coreboot does not accept github pull requests, but allows browsing and downloading the coreboot source.
Payloads
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://doc.coreboot.org/payloads.html for a list of some of coreboot's supported payloads.
Supported Hardware
The coreboot project supports a wide range of architectures, chipsets, devices, and mainboards. While not all of these are documented, you can find some information in the Architecture-specific documentation or the SOC-specific documentation.
For details about the specific mainboard devices that coreboot supports, please consult the Mainboard-specific documentation or the Board Status pages.
Releases
Releases are currently done by coreboot every quarter. The release archives contain the entire coreboot codebase from the time of the release, along with any external submodules. The submodules containing binaries are separated from the general release archives. All of the packages required to build the coreboot toolchains are also kept at coreboot.org in case the websites change, or those specific packages become unavailable in the future.
All releases are available on the coreboot download page.
Please note that the coreboot releases are best considered as snapshots of the codebase, and do not currently guarantee any sort of extra stability.
Build Requirements and building coreboot
The coreboot build, associated utilities and payloads require many additional tools and packages to build. The actual coreboot binary is typically built using a coreboot-controlled toolchain to provide reproducibility across various platforms. It is also possible, though not recommended, to make it directly with your system toolchain. Operating systems and distributions come with an unknown variety of system tools and utilities installed. Because of this, it isn't reasonable to list all the required packages to do a build, but the documentation lists the requirements for a few different Linux distributions.
To see the list of tools and libraries, along with a list of instructions to get started building coreboot, go to the Starting from scratch tutorial page.
That same page goes through how to use QEMU to boot the build and see the output.
Website and Mailing List
Further details on the project, as well as links to documentation and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://doc.coreboot.org/community/forums.html
Copyrights and Licenses
Uncopyrightable files
There are many files in the coreboot tree that we feel are not copyrightable due to a lack of creative content.
"In order to qualify for copyright protection in the United States, a work must satisfy the originality requirement, which has two parts. The work must have “at least a modicum” of creativity, and it must be the independent creation of its author."
https://guides.lib.umich.edu/copyrightbasics/copyrightability
Similar terms apply to other locations.
These uncopyrightable files include:
- Empty files or files with only a comment explaining their existence. These may be required to exist as part of the build process but are not needed for the particular project.
- Configuration files either in binary or text form. Examples would be files such as .vbt files describing graphics configuration, .apcb files containing configuration parameters for AMD firmware binaries, and spd files as binary .spd or text *spd*.hex representing memory chip configuration.
- Machine-generated files containing version numbers, dates, hash values or other "non-creative" content.
As non-creative content, these files are in the public domain by default. As such, the coreboot project excludes them from the project's general license even though they may be included in a final binary.
If there are questions or concerns about this policy, please get in touch with the coreboot project via the mailing list.
Copyrights
The copyright on coreboot is owned by quite a large number of individual developers and companies. A list of companies and individuals with known copyright claims is present at the top level of the coreboot source tree in the 'AUTHORS' file. Please check the git history of each of the source files for details.
Licenses
Because of the way coreboot began, using a significant amount of source code from the Linux kernel, it's licensed the same way as the Linux Kernel, with GNU General Public License (GPL) Version 2. Individual files are licensed under various licenses, though all are compatible with GPLv2. The resulting coreboot image is licensed under the GPL, version 2. All source files should have an SPDX license identifier at the top for clarification.
Files under coreboot/Documentation/ are licensed under CC-BY 4.0 terms. As an exception, files under Documentation/ with a history older than 2017-05-24 might be under different licenses.
Files in the coreboot/src/commonlib/bsd directory are all licensed with the BSD-3-clause license. Many are also dual-licensed GPL-2.0-only or GPL-2.0-or-later. These files are intended to be shared with libpayload or other BSD licensed projects.
The libpayload project contained in coreboot/payloads/libpayload may be licensed as BSD or GPL, depending on the code pulled in during the build process. All GPL source code should be excluded unless the Kconfig option to include it is set.
The Software Freedom Conservancy
Since 2017, coreboot has been a member of The Software Freedom Conservancy, a nonprofit organization devoted to ethical technology and driving initiatives to make technology more inclusive. The conservancy acts as coreboot's fiscal sponsor and legal advisor.