soc/amd/common: Add I3C driver
Add an I3C driver that allows to use the I3C HW from the OS. It does: - Power on/off the I3C HW - Configures the IOMUX Add the SoC specific AOAC devices and GPIO pins to reconfigure the GPIO for I3C HW. New log messages are seen in coreboot: [DEBUG] MMIO: fedd2000 disabled TEST: The I3C driver loads on amd/glinda using Ubuntu 25.04. Change-Id: Ibca20e2a4f0cb0e6006cfa47fd4addbe27504645 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Patrick Rudolph
Felix Held
parent
cf5d6f1c88
commit
f4825e5c12
7 changed files with 101 additions and 31 deletions
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@ -1,28 +1,57 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/mmio.h>
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#include <acpi/acpigen.h>
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#include <amdblocks/aoac.h>
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#include <amdblocks/i2c.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <types.h>
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#if CONFIG(HAVE_ACPI_TABLES)
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static const char *i3c_acpi_name(const struct device *dev)
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static int get_i3c_bus_for_dev(const struct device *dev,
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const struct soc_i3c_ctrlr_info *ctrlr,
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const size_t num_ctrlrs)
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{
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size_t i;
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size_t num_ctrlrs;
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const struct soc_i3c_ctrlr_info *ctrlr = soc_get_i3c_ctrlr_info(&num_ctrlrs);
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if (!dev || !ctrlr)
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return -1;
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if (!(uintptr_t)dev->path.mmio.addr) {
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printk(BIOS_ERR, "NULL MMIO address at %s\n", __func__);
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return NULL;
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return -1;
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}
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for (i = 0; i < num_ctrlrs; i++) {
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if ((uintptr_t)dev->path.mmio.addr == ctrlr[i].bar)
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return ctrlr[i].acpi_name;
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for (int i = 0; i < num_ctrlrs; i++) {
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if (dev->path.mmio.addr != ctrlr[i].bar)
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continue;
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return i;
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}
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printk(BIOS_ERR, "%s: Could not find %lu\n", __func__, (uintptr_t)dev->path.mmio.addr);
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printk(BIOS_ERR, "%s: Could not find i3c bus for %s\n", __func__, dev_path(dev));
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return -1;
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}
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static const struct soc_i3c_ctrlr_info *
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get_i3c_info_for_dev(const struct device *dev)
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{
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size_t num_ctrlrs;
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const struct soc_i3c_ctrlr_info *ctrlr = soc_get_i3c_ctrlr_info(&num_ctrlrs);
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const int bus = get_i3c_bus_for_dev(dev, ctrlr, num_ctrlrs);
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if (ctrlr && bus >= 0 && bus < num_ctrlrs)
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return &ctrlr[bus];
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printk(BIOS_ERR, "%s: Could not find soc_i3c_ctrlr_info for %s\n", __func__, dev_path(dev));
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return NULL;
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}
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#if CONFIG(HAVE_ACPI_TABLES)
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static const char *i3c_acpi_name(const struct device *dev)
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{
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const struct soc_i3c_ctrlr_info *info = get_i3c_info_for_dev(dev);
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if (info)
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return info->acpi_name;
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printk(BIOS_ERR, "%s: Could not find soc_i3c_ctrlr_info for %s\n", __func__, dev_path(dev));
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return NULL;
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}
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@ -34,12 +63,47 @@ static void i3c_acpi_fill_ssdt(const struct device *dev)
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}
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#endif
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/* Even though this is called enable, it gets called for both enabled and disabled devices. */
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static void i3c_enable(struct device *dev)
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{
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const struct soc_i3c_ctrlr_info *info = get_i3c_info_for_dev(dev);
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if (!info)
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return;
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if (dev->enabled) {
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power_on_aoac_device(info->aoac_device);
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wait_for_aoac_enabled(info->aoac_device);
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} else {
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power_off_aoac_device(info->aoac_device);
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}
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}
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static void i3c_init(struct device *dev)
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{
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size_t num_ctrlrs, num_buses;
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const struct soc_i3c_ctrlr_info *ctrlr = soc_get_i3c_ctrlr_info(&num_ctrlrs);
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const int bus = get_i3c_bus_for_dev(dev, ctrlr, num_ctrlrs);
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if (bus < 0)
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return;
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const struct dw_i2c_bus_config *cfg = soc_get_i2c_bus_config(&num_buses);
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if (cfg)
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soc_i2c_misc_init(bus, cfg);
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}
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static void i3c_read_resources(struct device *dev)
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{
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mmio_range(dev, 0, dev->path.mmio.addr, 4 * KiB);
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}
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/*
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* Currently there's no I3C driver, thus the I3C hardware cannot be used pre ramstage.
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* It's sufficient to power switch the I3C controllers in the enable method.
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*/
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struct device_operations soc_amd_i3c_mmio_ops = {
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.enable = i3c_enable,
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.init = i3c_init,
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.read_resources = i3c_read_resources,
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.set_resources = noop_set_resources,
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#if CONFIG(HAVE_ACPI_TABLES)
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@ -74,6 +74,7 @@ struct i2c_pad_control {
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struct soc_i3c_ctrlr_info {
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uintptr_t bar;
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const char *acpi_name;
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unsigned int aoac_device;
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};
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void fch_i2c_pad_init(unsigned int bus,
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@ -1,14 +1,15 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/i2c.h>
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#include <soc/aoac_defs.h>
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#include <soc/iomap.h>
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#include <types.h>
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static const struct soc_i3c_ctrlr_info i3c_ctrlr[I3C_CTRLR_COUNT] = {
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{ APU_I3C0_BASE, "I3C0" },
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{ APU_I3C1_BASE, "I3C1" },
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{ APU_I3C2_BASE, "I3C2" },
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{ APU_I3C3_BASE, "I3C3" }
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{ APU_I3C0_BASE, "I3C0", FCH_AOAC_DEV_I3C0},
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{ APU_I3C1_BASE, "I3C1", FCH_AOAC_DEV_I3C1},
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{ APU_I3C2_BASE, "I3C2", FCH_AOAC_DEV_I3C2},
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{ APU_I3C3_BASE, "I3C3", FCH_AOAC_DEV_I3C3}
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};
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const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs)
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@ -1,14 +1,15 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/i2c.h>
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#include <soc/aoac_defs.h>
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#include <soc/iomap.h>
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#include <types.h>
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static const struct soc_i3c_ctrlr_info i3c_ctrlr[I3C_CTRLR_COUNT] = {
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{ APU_I3C0_BASE, "I3C0" },
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{ APU_I3C1_BASE, "I3C1" },
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{ APU_I3C2_BASE, "I3C2" },
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{ APU_I3C3_BASE, "I3C3" }
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{ APU_I3C0_BASE, "I3C0", FCH_AOAC_DEV_I3C0},
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{ APU_I3C1_BASE, "I3C1", FCH_AOAC_DEV_I3C1},
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{ APU_I3C2_BASE, "I3C2", FCH_AOAC_DEV_I3C2},
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{ APU_I3C3_BASE, "I3C3", FCH_AOAC_DEV_I3C3}
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};
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const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs)
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@ -1,14 +1,15 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/i2c.h>
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#include <soc/aoac_defs.h>
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#include <soc/iomap.h>
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#include <types.h>
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static const struct soc_i3c_ctrlr_info i3c_ctrlr[I3C_CTRLR_COUNT] = {
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{ APU_I3C0_BASE, "I3C0" },
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{ APU_I3C1_BASE, "I3C1" },
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{ APU_I3C2_BASE, "I3C2" },
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{ APU_I3C3_BASE, "I3C3" }
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{ APU_I3C0_BASE, "I3C0", FCH_AOAC_DEV_I3C0},
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{ APU_I3C1_BASE, "I3C1", FCH_AOAC_DEV_I3C1},
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{ APU_I3C2_BASE, "I3C2", FCH_AOAC_DEV_I3C2},
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{ APU_I3C3_BASE, "I3C3", FCH_AOAC_DEV_I3C3}
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};
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const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs)
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@ -1,14 +1,15 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/i2c.h>
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#include <soc/aoac_defs.h>
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#include <soc/iomap.h>
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#include <types.h>
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static const struct soc_i3c_ctrlr_info i3c_ctrlr[I3C_CTRLR_COUNT] = {
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{ APU_I3C0_BASE, "I3C0" },
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{ APU_I3C1_BASE, "I3C1" },
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{ APU_I3C2_BASE, "I3C2" },
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{ APU_I3C3_BASE, "I3C3" }
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{ APU_I3C0_BASE, "I3C0", FCH_AOAC_DEV_I3C0},
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{ APU_I3C1_BASE, "I3C1", FCH_AOAC_DEV_I3C1},
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{ APU_I3C2_BASE, "I3C2", FCH_AOAC_DEV_I3C2},
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{ APU_I3C3_BASE, "I3C3", FCH_AOAC_DEV_I3C3}
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};
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const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs)
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@ -1,14 +1,15 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/i2c.h>
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#include <soc/aoac_defs.h>
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#include <soc/iomap.h>
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#include <types.h>
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static const struct soc_i3c_ctrlr_info i3c_ctrlr[I3C_CTRLR_COUNT] = {
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{ APU_I3C0_BASE, "I3C0" },
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{ APU_I3C1_BASE, "I3C1" },
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{ APU_I3C2_BASE, "I3C2" },
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{ APU_I3C3_BASE, "I3C3" }
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{ APU_I3C0_BASE, "I3C0", FCH_AOAC_DEV_I3C0},
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{ APU_I3C1_BASE, "I3C1", FCH_AOAC_DEV_I3C1},
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{ APU_I3C2_BASE, "I3C2", FCH_AOAC_DEV_I3C2},
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{ APU_I3C3_BASE, "I3C3", FCH_AOAC_DEV_I3C3}
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};
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const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs)
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