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soc/intel/pantherlake: Switch to common eSPI/LPC initialization

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Replace platform-specific espi.c with the common eSPI/LPC
initialization driver.

Changes:
- Remove src/soc/intel/pantherlake/espi.c
- Enable SOC_INTEL_COMMON_FEATURE_ESPI in Kconfig
- Update Makefile.mk to remove espi.c from build

The eSPI/LPC initialization was nearly identical across platforms,
differing only in minor header inclusions and ENV_RAMSTAGE wrapper
usage. The common implementation uses the config_t typedef that
each platform defines, providing clean abstraction without
preprocessor conditionals.

TEST=Build and boot to the OS on a Fatcat device

Change-Id: If5f2de9faa209ff30f986f34b1816ffa6d5fc683
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91219
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jeremy Compostella 2026-02-26 09:38:57 -08:00 • committed by Matt DeVillier
commit 7278030fa6
3 changed files with 1 additions and 51 deletions
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1
src/soc/intel/pantherlake/Kconfig
View file

@ -97,6 +97,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
select SOC_INTEL_COMMON_BLOCK_XHCI
select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
select SOC_INTEL_COMMON_FEATURE
select SOC_INTEL_COMMON_FEATURE_ESPI
select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN

3
src/soc/intel/pantherlake/Makefile.mk
View file

@ -13,10 +13,8 @@ all-y += gpio.c
bootblock-y += bootblock/bootblock.c
bootblock-y += bootblock/pcd.c
bootblock-y += bootblock/report_platform.c
bootblock-y += espi.c
romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += cse_telemetry.c
romstage-y += espi.c
romstage-y += meminit.c
romstage-y += pcie_rp.c
romstage-y += reset.c
@ -28,7 +26,6 @@ ramstage-y += chip.c
ramstage-y += cpu.c
ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c
ramstage-y += elog.c
ramstage-y += espi.c
ramstage-y += finalize.c
ramstage-y += fsp_params.c
ramstage-y += lockdown.c

48
src/soc/intel/pantherlake/espi.c
View file

@ -1,48 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/pci.h>
#include <pc80/isa-dma.h>
#include <pc80/i8259.h>
#include <arch/ioapic.h>
#include <intelblocks/itss.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/pcr.h>
#include <intelpch/espi.h>
#include <soc/iomap.h>
#include <soc/irq.h>
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
#include <soc/soc_chip.h>
#include <static.h>
void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
{
const struct soc_intel_pantherlake_config *config = config_of_soc();
gen_io_dec[0] = config->gen1_dec;
gen_io_dec[1] = config->gen2_dec;
gen_io_dec[2] = config->gen3_dec;
gen_io_dec[3] = config->gen4_dec;
}
void lpc_soc_init(struct device *dev)
{
/* Legacy initialization */
isa_dma_init();
pch_misc_init();
/* Enable CLKRUN_EN for power gating ESPI */
lpc_enable_pci_clk_cntl();
/* Set ESPI Serial IRQ mode */
if (CONFIG(SERIRQ_CONTINUOUS_MODE))
lpc_set_serirq_mode(SERIRQ_CONTINUOUS);
else
lpc_set_serirq_mode(SERIRQ_QUIET);
/* Interrupt configuration */
pch_enable_ioapic();
pch_pirq_init();
setup_i8259();
i8259_configure_irq_trigger(9, 1);
}