soc/intel/jasperlake: Switch to common eSPI/LPC initialization

Replace platform-specific espi.c with the common eSPI/LPC
initialization driver.

Changes:
- Remove src/soc/intel/jasperlake/espi.c
- Enable SOC_INTEL_COMMON_FEATURE_ESPI in Kconfig
- Update Makefile.mk to remove espi.c from build

The eSPI/LPC initialization was nearly identical across platforms,
differing only in minor header inclusions and ENV_RAMSTAGE wrapper
usage. The common implementation uses the config_t typedef that
each platform defines, providing clean abstraction without
preprocessor conditionals.

Change-Id: Ied29a5f2dabdebe0afedd1d69e4a817d6606a82d
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>

src/soc/intel/jasperlake/Kconfig

@@ -56,6 +56,7 @@ config SOC_INTEL_JASPERLAKE
 	select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_ESPI
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN

src/soc/intel/jasperlake/Makefile.mk

@@ -11,11 +11,9 @@ all-y += pmutil.c
 bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/pch.c
 bootblock-y += bootblock/report_platform.c
-bootblock-y += espi.c
 bootblock-y += gpio.c
 bootblock-y += p2sb.c
 
-romstage-y += espi.c
 romstage-y += gpio.c
 romstage-y += meminit.c
 romstage-y += pcie_rp.c
@@ -25,7 +23,6 @@ ramstage-y += acpi.c
 ramstage-y += chip.c
 ramstage-y += cpu.c
 ramstage-y += elog.c
-ramstage-y += espi.c
 ramstage-y += finalize.c
 ramstage-y += fsp_params.c
 ramstage-y += gpio.c

src/soc/intel/jasperlake/espi.c

@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <pc80/isa-dma.h>
-#include <pc80/i8259.h>
-#include <device/pci_ops.h>
-#include <arch/ioapic.h>
-#include <intelblocks/itss.h>
-#include <intelblocks/lpc_lib.h>
-#include <intelpch/espi.h>
-#include <soc/iomap.h>
-#include <soc/irq.h>
-#include <soc/pci_devs.h>
-#include <soc/pcr_ids.h>
-#include <soc/soc_chip.h>
-#include <static.h>
-
-void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
-{
-	const config_t *config = config_of_soc();
-
-	gen_io_dec[0] = config->gen1_dec;
-	gen_io_dec[1] = config->gen2_dec;
-	gen_io_dec[2] = config->gen3_dec;
-	gen_io_dec[3] = config->gen4_dec;
-}
-
-#if ENV_RAMSTAGE
-void lpc_soc_init(struct device *dev)
-{
-	/* Legacy initialization */
-	isa_dma_init();
-	pch_misc_init();
-
-	/* Enable CLKRUN_EN for power gating ESPI */
-	lpc_enable_pci_clk_cntl();
-
-	/* Set ESPI Serial IRQ mode */
-	if (CONFIG(SERIRQ_CONTINUOUS_MODE))
-		lpc_set_serirq_mode(SERIRQ_CONTINUOUS);
-	else
-		lpc_set_serirq_mode(SERIRQ_QUIET);
-
-	/* Interrupt configuration */
-	pch_enable_ioapic();
-	pch_pirq_init();
-	setup_i8259();
-	i8259_configure_irq_trigger(9, 1);
-}
-
-#endif