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soc/intel/alderlake: Use common SoundWire driver

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Migrate Alder Lake to use the common SoundWire driver implementation
from the Intel common feature code. This change eliminates platform-
specific code by leveraging the shared soundwire.c driver.

This commit:
- Selects SOC_INTEL_COMMON_FEATURE_SOUNDWIRE Kconfig
- Removes src/soc/intel/alderlake/soundwire.c
- Updates Makefile to remove soundwire.c compilation

Alder Lake uses the default values (4 SoundWire master links with ACPI
address 0x40000000).

Change-Id: Idf21d32d0cab9e3c6ca35e2b9f20c42c0455b5bb
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
This commit is contained in:
Jeremy Compostella 2026-02-26 09:16:31 -08:00 • committed by Matt DeVillier
commit ef364d623d
3 changed files with 1 additions and 72 deletions
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1
src/soc/intel/alderlake/Kconfig
View file

@ -86,6 +86,7 @@ config SOC_INTEL_ALDERLAKE
select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
select SOC_INTEL_COMMON_FEATURE
select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF
select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN

1
src/soc/intel/alderlake/Makefile.mk
View file

@ -35,7 +35,6 @@ ramstage-y += pcie_rp.c
ramstage-y += pmc.c
ramstage-y += reset.c
ramstage-$(CONFIG_SOC_INTEL_ALDERLAKE_TCSS_USB4_SUPPORT) += retimer.c
ramstage-y += soundwire.c
ramstage-y += systemagent.c
ramstage-y += tcss.c
ramstage-y += vr_config.c

71
src/soc/intel/alderlake/soundwire.c
View file

@ -1,71 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi_soundwire.h>
#include <console/console.h>
#include <device/mmio.h>
#include <device/soundwire.h>
#include <drivers/intel/soundwire/soundwire.h>
#include <intelblocks/pmclib.h>
#include <stddef.h>
#include <string.h>
static const struct soundwire_link link_xtal_38_4 = {
.clock_stop_mode0_supported = 1,
.clock_stop_mode1_supported = 1,
.clock_frequencies_supported_count = 1,
.clock_frequencies_supported = { 4800 * KHz },
.default_frame_rate = 48 * KHz,
.default_frame_row_size = 50,
.default_frame_col_size = 4,
.dynamic_frame_shape = 1,
.command_error_threshold = 16,
};
static const struct soundwire_link link_xtal_24 = {
.clock_stop_mode0_supported = 1,
.clock_stop_mode1_supported = 1,
.clock_frequencies_supported_count = 1,
.clock_frequencies_supported = { 6 * MHz },
.default_frame_rate = 48 * KHz,
.default_frame_row_size = 125,
.default_frame_col_size = 2,
.dynamic_frame_shape = 1,
.command_error_threshold = 16,
};
static struct intel_soundwire_controller intel_controller = {
.acpi_address = 0x40000000,
.sdw = {
.master_list_count = 4
}
};
int soc_fill_soundwire_controller(struct intel_soundwire_controller **controller)
{
const struct soundwire_link *link;
enum pch_pmc_xtal xtal = pmc_get_xtal_freq();
size_t i;
/* Select link config based on XTAL frequency and set IP clock. */
switch (xtal) {
case XTAL_24_MHZ:
link = &link_xtal_24;
intel_controller.ip_clock = 24 * MHz;
break;
case XTAL_38_4_MHZ:
link = &link_xtal_38_4;
intel_controller.ip_clock = 38400 * KHz;
break;
case XTAL_19_2_MHZ:
default:
printk(BIOS_ERR, "%s: XTAL not supported: 0x%x\n", __func__, xtal);
return -1;
}
/* Fill link config in controller map based on selected XTAL. */
for (i = 0; i < intel_controller.sdw.master_list_count; i++)
memcpy(&intel_controller.sdw.master_list[i], link, sizeof(*link));
*controller = &intel_controller;
return 0;
}