Haswell NRI: Implement 1D margin training
Implement an algorithm that performs a simple 1D margin training. This algorithm is generic, i.e. it can be used with multiple margin params. Use this algorithm to train three margin parameters: RdT, WrT and RdV. This algorithm also does per-bit calibration, but only for RdT and WrT since Haswell does not have per-rank per-bit RdV (c.f. `RX_OFFSET_VDQ` register). Still, implement support in `change_margin()` for all three types of per-bit margins (WrTBit, RdTBit, RdVBit) for completeness. Tested on Asrock Z97 Extreme6 with 2 DIMMs per channel (1R + 2R): - NRI finishes successfully, board still boots to Arch Linux. - Both fast training as well as S3 suspend/resume still work. Change-Id: I382cea8e230aee46a0dc66248f1e678d8a9a0090 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89314 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
Matt DeVillier
parent
098a5cf16e
commit
08f2f3a21b
7 changed files with 496 additions and 8 deletions
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@ -18,6 +18,7 @@ romstage-y += setup_wdb.c
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romstage-y += spd_bitmunching.c
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romstage-y += testing_io.c
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romstage-y += timings_refresh.c
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romstage-y += train_1d_margins.c
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romstage-y += train_jedec_write_leveling.c
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romstage-y += train_read_mpr.c
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romstage-y += train_receive_enable.c
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@ -200,18 +200,109 @@ static void update_data_offset_train(
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}
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}
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static uint32_t get_max_margin(const enum margin_parameter param)
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static uint16_t get_per_bit_reg(
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const enum margin_parameter param,
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const bool multicast,
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const uint8_t channel,
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const uint8_t rank,
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const uint8_t byte)
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{
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switch (param) {
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case RdTBit:
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if (multicast) {
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return DDR_DATA_RX_PER_BIT_RANK(rank);
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} else {
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return RX_PER_BIT(channel, rank, byte);
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}
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case WrTBit:
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if (multicast) {
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return DDR_DATA_TX_PER_BIT_RANK(rank);
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} else {
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return TX_PER_BIT(channel, rank, byte);
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}
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case RdVBit:
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/** TODO: Broadwell has per-rank RX_OFFSET_VDQ registers **/
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if (multicast) {
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return DDR_DATA_RX_OFFSET_VDQ;
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} else {
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return RX_OFFSET_VDQ(channel, byte);
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}
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default:
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die("%s: Invalid margin parameter %d\n", __func__, param);
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}
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}
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static void update_per_bit_margin(
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struct sysinfo *ctrl,
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const enum margin_parameter param,
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const uint8_t channel,
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const uint8_t rank,
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const uint8_t byte,
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const uint32_t value)
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{
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for (uint8_t bit = 0; bit < NUM_BITS; bit++) {
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const uint8_t v_bit = value >> (4 * bit) & 0xf;
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switch (param) {
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case RdTBit:
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ctrl->rxdqpb[channel][rank][byte][bit].center = v_bit;
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break;
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case WrTBit:
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ctrl->txdqpb[channel][rank][byte][bit].center = v_bit;
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break;
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case RdVBit:
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ctrl->rxdqvrefpb[channel][rank][byte][bit].center = v_bit;
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break;
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default:
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break;
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}
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}
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}
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static void change_per_bit_margin(
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struct sysinfo *ctrl,
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const enum margin_parameter param,
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const bool multicast,
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const uint8_t in_channel,
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const uint8_t rank,
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const uint8_t in_byte,
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const bool update_ctrl,
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const uint32_t value,
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const enum regfile_mode regfile)
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{
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const bool is_rd = param == RdTBit || param == RdVBit;
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const bool is_wr = param == WrTBit;
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const uint16_t reg = get_per_bit_reg(param, multicast, in_channel, rank, in_byte);
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mchbar_write32(reg, value);
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if (multicast) {
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for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
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if (!does_ch_exist(ctrl, channel))
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continue;
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download_regfile(ctrl, channel, true, rank, regfile, 0, is_rd, is_wr);
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if (!update_ctrl)
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continue;
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for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
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update_per_bit_margin(ctrl, param, channel, rank, byte, value);
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}
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}
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} else {
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download_regfile(ctrl, in_channel, false, rank, regfile, in_byte, is_rd, is_wr);
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if (!update_ctrl)
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return;
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update_per_bit_margin(ctrl, param, in_channel, rank, in_byte, value);
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}
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}
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uint32_t get_max_margin_for_param(const enum margin_parameter param)
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{
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switch (param) {
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case RcvEna:
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case RdT:
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case WrT:
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case WrDqsT:
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return MAX_POSSIBLE_TIME;
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case RdV:
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case WrV:
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return MAX_POSSIBLE_VREF;
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default:
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die("%s: Invalid margin parameter %u\n", __func__, param);
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return MAX_POSSIBLE_TIME;
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}
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}
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@ -233,7 +324,22 @@ void change_margin(
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if (!en_multicast && !does_ch_exist(ctrl, channel))
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die("%s: Tried to change margin of empty channel %u\n", __func__, channel);
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const uint32_t max_value = get_max_margin(param);
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/* Per-bit margins are handled differently */
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if (param == WrTBit || param == RdTBit || param == RdVBit) {
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change_per_bit_margin(
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ctrl,
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param,
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en_multicast,
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channel,
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rank,
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byte,
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update_ctrl,
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(uint32_t)value0,
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regfile);
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return;
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}
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const uint32_t max_value = get_max_margin_for_param(param);
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const int32_t v0 = clamp_s32(-max_value, value0, max_value);
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union ddr_data_offset_train_reg ddr_data_offset_train = {
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@ -129,6 +129,9 @@ static const struct task_entry cold_boot[] = {
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{ train_receive_enable, true, "RCVET", },
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{ train_read_mpr, true, "RDMPRT", },
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{ train_jedec_write_leveling, true, "JWRL", },
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{ train_write_timing_centering, true, "WRTC1D", },
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{ train_read_timing_centering, true, "RDTC1D", },
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{ train_read_voltage_centering, true, "RDVC1D", },
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{ optimise_comp, true, "OPTCOMP", },
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{ post_training, true, "POSTTRAIN", },
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{ activate_mc, true, "ACTIVATE", },
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@ -68,6 +68,29 @@ enum margin_parameter {
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WrT,
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WrDqsT,
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RdV,
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WrV,
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WrLevel,
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WrTBit,
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RdTBit,
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RdVBit,
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INVALID_MARGIN,
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};
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/*
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* This enum is used to index an array of margin results. Those are
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* used to keep track of available margin in more advanced training
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* algorithms (optimisation), c.f. margin_result member in sysinfo.
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*/
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enum last_margin_param {
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LastRxV,
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LastRxT,
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LastTxV,
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LastTxT,
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LastRcvEna,
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LastWrLevel,
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LastCmdT,
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LastCmdV,
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MAX_RESULT_TYPE,
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};
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enum opt_param {
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@ -232,6 +255,7 @@ enum raminit_status {
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RAMINIT_STATUS_SUCCESS = 0,
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RAMINIT_STATUS_NO_MEMORY_INSTALLED,
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RAMINIT_STATUS_UNSUPPORTED_MEMORY,
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RAMINIT_STATUS_INVALID_PARAMETER,
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RAMINIT_STATUS_MPLL_INIT_FAILURE,
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RAMINIT_STATUS_POLL_TIMEOUT,
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RAMINIT_STATUS_REUT_ERROR,
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@ -239,6 +263,7 @@ enum raminit_status {
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RAMINIT_STATUS_RCVEN_FAILURE,
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RAMINIT_STATUS_RMPR_FAILURE,
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RAMINIT_STATUS_JWRL_FAILURE,
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RAMINIT_STATUS_1D_MARGINING_FAILURE,
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RAMINIT_STATUS_INVALID_CACHE,
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RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
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};
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@ -261,12 +286,32 @@ struct raminit_dimm_info {
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bool valid;
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};
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struct last_margin {
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uint32_t start;
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uint32_t end;
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};
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struct time_margin {
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uint8_t left;
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uint8_t center;
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uint8_t right;
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};
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struct vref_margin {
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uint8_t low;
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uint8_t center;
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uint8_t high;
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};
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union raw_bitlane_errors {
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struct {
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uint32_t lower;
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uint32_t upper;
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uint8_t ecc;
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};
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uint8_t per_byte[NUM_LANES];
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};
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struct sysinfo {
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enum raminit_boot_mode bootmode;
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enum generic_stepping stepping;
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@ -355,6 +400,9 @@ struct sysinfo {
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uint8_t rxdqsn[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
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int8_t rxvref[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
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struct time_margin rxdqpb[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES][NUM_BITS];
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struct time_margin txdqpb[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES][NUM_BITS];
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struct vref_margin rxdqvrefpb[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES][NUM_BITS];
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uint8_t clk_pi_code[NUM_CHANNELS][NUM_SLOTRANKS];
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@ -365,6 +413,11 @@ struct sysinfo {
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uint8_t cmd_north_pi_code[NUM_CHANNELS][NUM_GROUPS];
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uint8_t cmd_south_pi_code[NUM_CHANNELS][NUM_GROUPS];
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/*
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* BIG WARNING: The slotrank comes before the channel!
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*/
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struct last_margin results[MAX_RESULT_TYPE][NUM_SLOTRANKS][NUM_CHANNELS][NUM_LANES];
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union tc_bank_reg tc_bank[NUM_CHANNELS];
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union tc_bank_rank_a_reg tc_bankrank_a[NUM_CHANNELS];
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union tc_bank_rank_b_reg tc_bankrank_b[NUM_CHANNELS];
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@ -488,6 +541,9 @@ enum raminit_status train_sense_amp_offset(struct sysinfo *ctrl);
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enum raminit_status train_receive_enable(struct sysinfo *ctrl);
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enum raminit_status train_read_mpr(struct sysinfo *ctrl);
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enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl);
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enum raminit_status train_read_timing_centering(struct sysinfo *ctrl);
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enum raminit_status train_write_timing_centering(struct sysinfo *ctrl);
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enum raminit_status train_read_voltage_centering(struct sysinfo *ctrl);
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enum raminit_status optimise_comp(struct sysinfo *ctrl);
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enum raminit_status save_training_values(struct sysinfo *ctrl);
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enum raminit_status restore_training_values(struct sysinfo *ctrl);
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@ -536,6 +592,7 @@ void reut_issue_mrs_all(
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const uint16_t val[NUM_SLOTS]);
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enum raminit_status reut_issue_zq(struct sysinfo *ctrl, uint8_t chanmask, uint8_t zq_type);
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union raw_bitlane_errors get_bitlane_errors(const uint8_t channel);
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void write_wdb_fixed_pat(
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const struct sysinfo *ctrl,
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@ -604,6 +661,8 @@ void download_regfile(
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bool read_rf_rd,
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bool read_rf_wr);
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uint32_t get_max_margin_for_param(const enum margin_parameter param);
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void change_margin(
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struct sysinfo *ctrl,
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const enum margin_parameter param,
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@ -194,3 +194,12 @@ enum raminit_status reut_issue_zq(struct sysinfo *ctrl, uint8_t chanmask, uint8_
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return status;
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}
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union raw_bitlane_errors get_bitlane_errors(const uint8_t channel)
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{
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return (union raw_bitlane_errors) {
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.lower = mchbar_read32(REUT_ch_ERR_DATA_STATUS(channel) + 0),
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.upper = mchbar_read32(REUT_ch_ERR_DATA_STATUS(channel) + 4),
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.ecc = mchbar_read8(REUT_ch_ERR_MISC_STATUS(channel)),
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};
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}
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305
src/northbridge/intel/haswell/native_raminit/train_1d_margins.c
Normal file
305
src/northbridge/intel/haswell/native_raminit/train_1d_margins.c
Normal file
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@ -0,0 +1,305 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include "raminit_native.h"
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#include "ranges.h"
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#define MAX_BITLANE_LINES (2 * MAX_POSSIBLE_BOTH + 1)
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#define MARGIN_MIN_WIDTH 8
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#define MARGIN_1D_PLOT RAM_DEBUG
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static void print_bitlane(
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struct sysinfo *ctrl,
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const uint8_t channel,
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const int32_t m_start,
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const int32_t m_step,
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const int32_t m_stop,
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const union raw_bitlane_errors bit_failures[NUM_CHANNELS][MAX_BITLANE_LINES])
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{
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for (int32_t offset = m_start; offset <= m_stop; offset += m_step) {
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const uint32_t index = offset + MAX_POSSIBLE_BOTH;
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const union raw_bitlane_errors *failures = &bit_failures[channel][index];
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printk(MARGIN_1D_PLOT, "\n% 5d\t", offset);
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for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
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const uint8_t byte_errors = failures->per_byte[byte];
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for (uint8_t bit = 0; bit < NUM_BITS; bit++)
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printk(MARGIN_1D_PLOT, byte_errors & BIT(bit) ? "#" : ".");
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}
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}
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}
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static enum raminit_status apply_dq_offsets(
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struct sysinfo *ctrl,
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const uint8_t channel,
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const uint8_t rank,
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const enum margin_parameter param,
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enum raminit_status status,
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const struct linear_train_data chan_data[])
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{
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printk(BIOS_DEBUG, "\nC%u.R%u: Left\tRight\tWidth\tCenter\n", channel, rank);
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for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
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const struct linear_train_data *const curr_data = &chan_data[byte];
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const int32_t lwidth = range_width(curr_data->largest);
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const int32_t center = range_center(curr_data->largest);
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printk(BIOS_DEBUG, " B%u: %d\t%d\t%d\t%d",
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byte,
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curr_data->largest.start,
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curr_data->largest.end,
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lwidth,
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center);
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if (lwidth < MARGIN_MIN_WIDTH) {
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printk(BIOS_ERR,
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"\t1D eye too small! channel: %u byte: %u width: %d\n",
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channel, byte, lwidth);
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status = RAMINIT_STATUS_1D_MARGINING_FAILURE;
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} else {
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printk(BIOS_DEBUG, "\n");
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}
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const struct last_margin margin = {
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.start = ABS(curr_data->largest.start - center) * 10,
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.end = ABS(curr_data->largest.end - center) * 10,
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};
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switch (param) {
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case RdT:
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ctrl->rxdqsp[channel][rank][byte] += center;
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ctrl->rxdqsn[channel][rank][byte] += center;
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update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
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ctrl->results[LastRxT][rank][channel][byte] = margin;
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break;
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case WrT:
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ctrl->tx_dq[channel][rank][byte] += center;
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update_txt(ctrl, channel, rank, byte, TXT_RESTORE, 0);
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ctrl->results[LastTxT][rank][channel][byte] = margin;
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break;
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case RdV:
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/* RdV training uses half steps */
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ctrl->rxvref[channel][rank][byte] += center / 2;
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update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
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ctrl->results[LastRxV][rank][channel][byte] = margin;
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break;
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default:
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break;
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}
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}
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return status;
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}
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static const char *const get_delay_string(const enum margin_parameter param)
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{
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switch (param) {
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case RdT: return "RdDqsDelay";
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case WrT: return "WrDqsDelay";
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case RdV: return "RdVoltage";
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default: return NULL;
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}
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}
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static enum margin_parameter get_per_bit_margin_param(const enum margin_parameter param)
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{
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switch (param) {
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case RdT: return RdTBit;
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case WrT: return WrTBit;
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case RdV: return RdVBit;
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default: return INVALID_MARGIN;
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}
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}
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static enum raminit_status train_1d_margin(
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struct sysinfo *ctrl,
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const uint8_t chanmask_in,
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const enum margin_parameter param,
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const bool reset_per_bit,
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const uint8_t loopcount)
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{
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const char *const delay_string = get_delay_string(param);
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if (!delay_string) {
|
||||
printk(BIOS_ERR, "%s: Invalid margin parameter %u\n", __func__, param);
|
||||
return RAMINIT_STATUS_INVALID_PARAMETER;
|
||||
}
|
||||
setup_io_test_basic_va(ctrl, chanmask_in, loopcount, NSOE);
|
||||
|
||||
const enum margin_parameter param_bit = get_per_bit_margin_param(param);
|
||||
if (reset_per_bit && param_bit == INVALID_MARGIN) {
|
||||
printk(BIOS_ERR, "%s: Invalid per-bit margin for param %u\n", __func__, param);
|
||||
return RAMINIT_STATUS_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
const int32_t m_stop = get_max_margin_for_param(param);
|
||||
const int32_t m_start = -m_stop;
|
||||
const int32_t m_step = 1;
|
||||
enum raminit_status status = 0;
|
||||
for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
|
||||
if (!does_rank_exist(ctrl, rank))
|
||||
continue;
|
||||
|
||||
/* Hell thinks this should be resetting the currently selected rank */
|
||||
if (reset_per_bit) {
|
||||
change_1d_margin_multicast(
|
||||
ctrl,
|
||||
param_bit,
|
||||
0x88888888,
|
||||
rank,
|
||||
true,
|
||||
REG_FILE_USE_RANK);
|
||||
}
|
||||
printk(BIOS_DEBUG, "Rank %u\n", rank);
|
||||
printk(MARGIN_1D_PLOT, "Channel");
|
||||
for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
if (!rank_in_ch(ctrl, rank, channel))
|
||||
continue;
|
||||
|
||||
printk(MARGIN_1D_PLOT, "\t%u\t\t", channel);
|
||||
}
|
||||
printk(MARGIN_1D_PLOT, "\nByte");
|
||||
for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
if (!rank_in_ch(ctrl, rank, channel))
|
||||
continue;
|
||||
|
||||
printk(MARGIN_1D_PLOT, "\t");
|
||||
for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
|
||||
printk(MARGIN_1D_PLOT, "%u ", byte);
|
||||
}
|
||||
uint8_t chanmask = 0;
|
||||
for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
chanmask |= select_reut_ranks(ctrl, channel, BIT(rank));
|
||||
if (!(BIT(channel) & chanmask))
|
||||
continue;
|
||||
|
||||
/* Update rank timing to middle value */
|
||||
for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
if (param == RdT) {
|
||||
ctrl->rxdqsp[channel][rank][byte] = 32;
|
||||
ctrl->rxdqsn[channel][rank][byte] = 32;
|
||||
update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
|
||||
} else if (param == WrT) {
|
||||
/*
|
||||
* Put TxDq in the middle of the strobe and ensure
|
||||
* there is enough room to sweep to the right.
|
||||
*/
|
||||
uint16_t tx_dq = ctrl->txdqs[channel][rank][byte] + 32;
|
||||
if ((tx_dq + m_stop) > 511)
|
||||
tx_dq = 511 - m_stop;
|
||||
|
||||
ctrl->tx_dq[channel][rank][byte] = tx_dq;
|
||||
update_txt(ctrl, channel, rank, byte, TXT_RESTORE, 0);
|
||||
} else if (param == RdV) {
|
||||
ctrl->rxvref[channel][rank][byte] = 0;
|
||||
update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
|
||||
}
|
||||
}
|
||||
|
||||
/* Set up REUT error counters to count errors per channel */
|
||||
mchbar_write32(REUT_ch_ERR_COUNTER_CTL_x(channel, 0), 0);
|
||||
}
|
||||
if (!chanmask)
|
||||
continue;
|
||||
|
||||
clear_data_offset_train_all(ctrl);
|
||||
printk(MARGIN_1D_PLOT, "\n%s", delay_string);
|
||||
struct linear_train_data region_data[NUM_CHANNELS][NUM_LANES] = { 0 };
|
||||
union raw_bitlane_errors bit_errors[NUM_CHANNELS][MAX_BITLANE_LINES] = { 0 };
|
||||
for (int32_t offset = m_start; offset <= m_stop; offset += m_step) {
|
||||
printk(MARGIN_1D_PLOT, "\n% 5d", offset);
|
||||
change_1d_margin_multicast(
|
||||
ctrl,
|
||||
param,
|
||||
offset,
|
||||
0,
|
||||
false,
|
||||
REG_FILE_USE_START);
|
||||
|
||||
run_io_test(ctrl, chanmask, ctrl->dq_pat, 1);
|
||||
for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
if (!(chanmask & BIT(channel)))
|
||||
continue;
|
||||
|
||||
/* Read out byte group error results and update limit */
|
||||
const uint16_t result = get_byte_group_errors(channel);
|
||||
bit_errors[channel][offset + MAX_POSSIBLE_BOTH] =
|
||||
get_bitlane_errors(channel);
|
||||
printk(MARGIN_1D_PLOT, "\t");
|
||||
for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
const bool pass = !(result & BIT(byte));
|
||||
printk(MARGIN_1D_PLOT, pass ? ". " : "# ");
|
||||
linear_record_pass(
|
||||
®ion_data[channel][byte],
|
||||
pass,
|
||||
offset,
|
||||
m_start,
|
||||
m_step);
|
||||
}
|
||||
}
|
||||
}
|
||||
printk(MARGIN_1D_PLOT, "\n\nBit lane information");
|
||||
for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
if (!(chanmask & BIT(channel)))
|
||||
continue;
|
||||
|
||||
printk(MARGIN_1D_PLOT, "\nChannel %u\nByte ", channel);
|
||||
for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
|
||||
printk(MARGIN_1D_PLOT, "%u ", byte);
|
||||
|
||||
printk(MARGIN_1D_PLOT, "\nBit ");
|
||||
for (uint8_t bit_count = 0; bit_count < ctrl->lanes * 8; bit_count++)
|
||||
printk(MARGIN_1D_PLOT, "%u", bit_count % 8);
|
||||
|
||||
printk(MARGIN_1D_PLOT, "\n%s", delay_string);
|
||||
print_bitlane(
|
||||
ctrl,
|
||||
channel,
|
||||
m_start,
|
||||
m_step,
|
||||
m_stop,
|
||||
bit_errors);
|
||||
|
||||
printk(MARGIN_1D_PLOT, "\n");
|
||||
}
|
||||
change_1d_margin_multicast(
|
||||
ctrl,
|
||||
param,
|
||||
0,
|
||||
0,
|
||||
false,
|
||||
REG_FILE_USE_CURRENT);
|
||||
|
||||
for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
if (!(chanmask & BIT(channel)))
|
||||
continue;
|
||||
|
||||
status = apply_dq_offsets(
|
||||
ctrl,
|
||||
channel,
|
||||
rank,
|
||||
param,
|
||||
status,
|
||||
region_data[channel]);
|
||||
}
|
||||
printk(BIOS_DEBUG, "\n");
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
#define DATA_TRAIN_LOOP_COUNT 15
|
||||
|
||||
enum raminit_status train_read_timing_centering(struct sysinfo *ctrl)
|
||||
{
|
||||
return train_1d_margin(ctrl, ctrl->chanmap, RdT, true, DATA_TRAIN_LOOP_COUNT);
|
||||
}
|
||||
|
||||
enum raminit_status train_write_timing_centering(struct sysinfo *ctrl)
|
||||
{
|
||||
return train_1d_margin(ctrl, ctrl->chanmap, WrT, true, DATA_TRAIN_LOOP_COUNT);
|
||||
}
|
||||
|
||||
enum raminit_status train_read_voltage_centering(struct sysinfo *ctrl)
|
||||
{
|
||||
/*
|
||||
* We do not reset per-bit RdV. Haswell only has one RX_OFFSET_VDQ register
|
||||
* per rank, so this would require combining training results for all ranks
|
||||
* somehow. While Broadwell and newer platforms have per-rank RX_OFFSET_VDQ
|
||||
* registers, we can keep using sense amp offset training results, for now.
|
||||
*/
|
||||
return train_1d_margin(ctrl, ctrl->chanmap, RdV, false, DATA_TRAIN_LOOP_COUNT);
|
||||
}
|
||||
|
|
@ -16,7 +16,9 @@
|
|||
|
||||
/* DDR DATA per-channel per-bytelane */
|
||||
#define RX_TRAIN_ch_r_b(ch, rank, byte) _DDRIO_C_R_B(0x0000, ch, rank, byte)
|
||||
#define RX_PER_BIT(ch, rank, byte) _DDRIO_C_R_B(0x0010, ch, rank, byte)
|
||||
#define TX_TRAIN_ch_r_b(ch, rank, byte) _DDRIO_C_R_B(0x0020, ch, rank, byte)
|
||||
#define TX_PER_BIT(ch, rank, byte) _DDRIO_C_R_B(0x0030, ch, rank, byte)
|
||||
|
||||
#define RX_OFFSET_VDQ(ch, byte) _DDRIO_C_R_B(0x004c, ch, 0, byte)
|
||||
|
||||
|
|
@ -126,8 +128,11 @@
|
|||
|
||||
#define REUT_ch_ERR_DATA_MASK(ch) _MCMAIN_C(0x40d8, ch)
|
||||
|
||||
#define REUT_ch_ERR_DATA_STATUS(ch) _MCMAIN_C(0x40e0, ch)
|
||||
#define REUT_ch_ERR_MISC_STATUS(ch) _MCMAIN_C(0x40e8, ch)
|
||||
|
||||
#define REUT_ch_ERR_COUNTER_CTL_x(ch, byte) _MCMAIN_C_X(0x40f0, ch, byte)
|
||||
|
||||
#define REUT_ch_MISC_CKE_CTRL(ch) _MCMAIN_C(0x4190, ch)
|
||||
#define REUT_ch_MISC_ODT_CTRL(ch) _MCMAIN_C(0x4194, ch)
|
||||
#define REUT_ch_MISC_PAT_CADB_CTRL(ch) _MCMAIN_C(0x4198, ch)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue