This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: Ia724e342651e064ca095f9f3f1153d86f0a73a46
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87159
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These boards do not support SATA, so this is not needed.
Change-Id: Iff9a30cf2e8b65649440b33f850f07d499baa073
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: I879819e028b71137010a21ddcc0ee6b1dafb7936
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These are not used so configure them accordingly.
Change-Id: I6c4d793210e3c869e4f500b18a1229c5c4d40f60
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These pins are not connected, so configure them accordingly.
Change-Id: I3cf06a0945a7793592e6599dfd4048a6114d1563
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add implementation of sku_id function that reports the SKU ID
information by making use of ChromeOS EC host command. This function
can replace redundant sku_id function definitions across boards that
rely on ChromeOS EC host command to report the SKU ID information.
The boards that relying on ChromeOS EC host command for SKU information
without any board specific quirks can select EC_GOOGLE_CHROMEEC_SKUID
to make use of common sku_id function.
Brya, zork, rex, fatcat, brox and dedede boards select
EC_GOOGLE_CHROMEEC_SKUID to use ChromeOS EC sku_id function.
BUG=b:396366352
TEST=Verify zork and brya boot log reports the correct the SKU ID
information
Change-Id: I958cc88bf316dd2327b6545c5a37e8010e96c5d7
Signed-off-by: Aamir Bohra <aamirbohra@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
ChromeEC support information for SKU, OEM name and manufacturer name
using EC host commands. Instead of tying it up with SKU ID Kconfig
define a new Kconfig that clearly describes and allow adding support
for SMBIOS APIs based on ChromeEC host command.
BUG=b:396366352
TEST=Verify ec_smbios still compiles for required boards.
Change-Id: I665a3276aa6dc01571657359d17f292efc601d63
Signed-off-by: Aamir Bohra <aamirbohra@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86993
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Consider special requirements for computing cache size in certain SoCs,
such as `soc/amd/glinda`.
Use the helper function to implement SoC-specific logic for computing
cache size.
Change-Id: I60707de4c8242a8fbda8cb5b791a1db762d94449
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit introduces support for touch functionalities on the
Google Fatcat board( Please see docu # 818597). Changes include:
- Configuration for building with the THC driver
- Support for touchscreen devices in both THC-I2C and THC-SPI modes
- Rework is necessary for touchscreen use in THC-SPI mode on Fatcat
board
- The ELAN BOM37A device is supported in THC-I2C mode
- The ELAN BOM36 device is supported in THC-SPI mode
- Support for the HYNITRON HFW68H touchpad device in THC-I2C mode
- A rework is required to switch the interrupt pad from GPP_A13 to
GPP_F18 for touchpad use in THC-I2C mode
- Introduction of variant-specific touch.h header file
- Wake support from S0ix state for both touchscreen and touchpad
across multiple modes: LPSS-I2C, THC-I2C, and THC-SPI
- PMC GPE DW0 is reconfigured to GPP_F for Touchpad in LPSS mode in
variant.c for wake support
BUG=none
TEST=
1. Set the CBI firmware configuration for touchscreen to
TOUCHSCREEN_LPSS_I2C and/or TOUCHPAD to TOUCHPAD_LPSS_I2C
2. Check the ACPI objects are generated in SSDT
3. The devices should be enumerated under the /sys/class/hidraw
directory
4. The Touchscreen and/or touchpad should function properly
The cursor on the screen should move accordingly
5. Test wake from S0ix state via touchscreen and touchpad inputs
6. Repeat the above for the THC CBI configurations:
touchscreen: TOUCHSCREEN_THC_I2C
touchpad: TOUCHPAD_THC_I2C
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I865dbb9eed648c8f35c7f469b27a13be993ff479
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85200
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change addresses an issue in the touch driver where the ACPI _PRW
method was added unconditionally. The ACPI _PRW method should only be
generated when an Interrupt() resource is used in the _CRS method.
When a GpioInt() resource is used instead, the _PRW method is not
required.
The ACPI generation code has been updated to conditionally add the
_PRW method based on whether the wake source is a GPIO interrupt or
an IRQ interrupt. Now, the _PRW method is only added when an IRQ pin
is specified, which is consistent with ACPI requirements.
BUG=none
TEST=Configure the DRIVERS_INTEL_TOUCH option on a motherboard that
has the necessary touch configurations with wake support. Verify that
the THC ACPI tables are correctly generated in the SSDT. If wake_gpio
(i.e. GpioInt()) is used for wake, no _PRW is generated for the device.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I56fc8486c7494ff37c1d580d57838fee286128a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87085
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SSD uses GPP_A20 for reset, and GPP_H07 for enable. Correct the GPIO
configuration and corresponding entry in the devicetree.
Change-Id: I71196f65883803ba9bfc8228bb74f25795bb3a6c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87127
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This GPIO is not connected, so configure it accordingly.
Change-Id: Idafd6fa727f6b3a9fbfe6543c53abeb736aa9f11
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87126
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure all strap GPIOs as outputs, rather than some being not
connected. This doesn't change anything, but is more explicit.
Set these all to sample on RSMRST.
Change-Id: I53415716364222de713b3bf967419e5a45322e69
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87125
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Also remove include folders that don't even exist.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ic64f5187e50b903af5461bfa4d57bb4951d3b501
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86864
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add NovaCustom V540TNx and V560TNx, which are variants of the mtl-h
baseboard, but with discrete graphics, compared to the igpu variant.
Other notable differences:
- 16" models come with TAS5825 Smart Amp
- Realtek RTL8111 network adapter
- 14" models have only one SSD slot
- The non-Thunderbolt USB-C port has DP Alt mode with displayport lanes
sourced from the discrete graphics
- HDMI port is wired to discrete graphics
NVIDIA dGPU ASL code will be added in subsequent patches.
TEST=Build V560TNx with UEFIPayload and boot to payload
Change-Id: I2b8194c486de1ba3e04aa74ed63caa7a151fbb8b
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Set AC / DC Load Line params. The values were dumped from original Clevo
Insyde UEFI firmware, version 1.07.02
Change-Id: I4cf729fc55ed6f2722606f393b6aa45afe396a6e
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86787
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable internal DMIC for francka.
Camera's DMIC is connected to the ALC256's DMIC pin.
BUG=b:396558772
TEST=Camera's DMIC works on francka.
Change-Id: Ie2b9fbd3d95cac145a4c64d9f07001d81880a0e5
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87034
Reviewed-by: Terry Cheong <htcheong@chromium.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
AMD64 spec refers to the field as MT (Message Type), but the IA64 spec
refers to it as DM (Delivery Mode). The problem is that there is another
field abbreviated as DM (Destination Mode) right next to it. So for
better readability, just stick to the AMD64 terminology.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I25cf69d555fe22526f128ff7ed41f82b71f2acf2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Add an allocation of an empty buffer for the Android protected virtual
machine firmware within cbmem. The buffer will be filled by the payload
and the purpose is to just reserve the memory. cbmem is used to make
sure that the region won't overlap with other reserved regions
or device regions.
BUG=b:354045389
BUG=b:359340876
TEST=depthcharge receives the buffer through lib_sysinfo
BRANCH=main
Change-Id: I48efc033ac0f5fbfcf3a52fabf40be016cd4c6f7
Signed-off-by: Bartłomiej Grzesik <bgrzesik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Update the SaGV frequency registers
- (`sagv_freq_mhz[1]`) in the devicetree from "3200" to "4800".
- (`sagv_freq_mhz[2]`) in the devicetree from "6000" to "6400".
- (`sagv_freq_mhz[3]`) in the devicetree from "6400" to "6800".
This change likely to improve the device performance.
BUG=b:328770565, b:407862619
TEST=Able to reduce the boot time by 18ms.
Change-Id: Id0b25adeed4b3f3e1c37d17901006a2db2d21223
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87087
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Correct XHCI and PHY register addresses and enable USB port 3 VBUS
to support USB host functionality.
BUG=b:379008996
BRANCH=none
TEST=build pass
Signed-off-by: Liu Liu <ot_liu.liu@mediatek.corp-partner.google.com>
Change-Id: I5f1b4b3eb178cb9a110b97a2763c8cff5cdf0ddd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87021
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Initialize SPI NOR Flash Controller (SNFC) in the bootblock to
enable CBFS and execute other stages such as verstage, romstage,
ramstage, etc.
BUG=b:379008996
BRANCH=none
TEST=Read NOR flash data successfully.
Signed-off-by: Noah Shen <noah.shen@mediatek.corp-partner.google.com>
Change-Id: Icf4af32dd9d8c704fd7246adda94dfa3350bb672
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This board does not have a DMIC, so don't try to disable.
Change-Id: Ic47f9c3b40dd76a78325b024ba8f93a117f7d031
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87095
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: Icfb80295ba0c55184b174a63756e8779111d9b76
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87122
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPP_F10 is not connected, so configure it accordingly.
Change-Id: I5a8fb34837b1b3f2f066ccc260f0ab749d7782c0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87121
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These are not connected to anything, so configure them accordingly.
Change-Id: Ia3a528faf74c23d0b78210b22c6e8d3f69de8184
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This GPIO is only used for full PCI wireless, and these boards use
CNVi so disconnect it.
Change-Id: Ie7be00543b5c99814204265157eeab654492724f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87119
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure all strap GPIOs as outputs, rather than some being not
connected. This doesn't change anything, but is more explicit.
Set these all to sample on RSMRST.
Change-Id: I0b0eb72c68d2fbe7920db798c2a625d7cc7e8063
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: Id0f00b9b4be06da1d58cfb4491eb7606cc968459
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87116
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: If1c102ecf9982dce1bd79175266451ed80da09f3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87115
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: Ia8a2ff8f370fef6249b1edbb08e00a01dedc3a07
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87113
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: Ibd60b124efa4f5cb0688ee097574884b9912fb66
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87112
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: I8dd5fade69b9e1c2b24b8ffaeac7f72e72894b9c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87111
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: I5ba2e400ec57a0c52523ea360bee17d9517454b5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87110
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: Ib86d4b0193fc78123ab3451e92865bff2bab5bd6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87106
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable `VBOOT_EARLY_EC_SYNC` for rull device. This enables EC software
sync in romstage. This is useful to achieve full USB-PD negotiation
early in the boot flow. It eliminates a problem seen in rull devices
where PMC is wrongly configured in depthcharge during the EC-sync
scenario which prevents USB devices from getting detected when
connected via a self-powered USB hub.
BUG=b:386920751
TEST=Verify detection and booting to OS from USB drive connected to the
Servo v4 debugger (self-powered hub) during the EC-sync scenario.
Change-Id: Ie36794a8a2c0bcd4ba77f3ad844a30f28f59403f
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
The parent project kuldax had support wifi sar switch.
But moxie does not support Wifi sar. Remove wifi sar table.
BUG=b:248367859
TEST=build pass
Change-Id: I012ff2d9c8c4d6d4480cae7166bf8e633bcaa752
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Dirks is chromebox, enable early graphics support for HDMI.
BUG=b:399236160
TEST=On-screen text message seen during MRC training on dirks
Change-Id: I8ab2c3a2cc72059facbbc0bba59cc480a5081a9e
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit modifies the handling of PCH High Definition Audio (HDA)
Serial Digital Interface (SDI) enablement.
- In `devicetree.cb`, the static `pch_hda_sdi_enable` property is
removed to allow varaints to override if needed.
- In `variant.c`, `variant_update_soc_memory_init_params` is
introduced to dynamically configure `PchHdaSdiEnable` UPD based on
the firmware configuration (for example: `AUDIO_ALC256_HDA` or
`AUDIO_ALC256M_CG_HDA`).
SDI is enabled if this FW config option is present. Otherwise, it
defaults to disabled.
- `variant.c` is now added for romstage as well because the SDI
configuration needs to happen earlier in the boot process.
BUG=b:328770565, b:407876136
TEST=Able to reduce the boot time by 18ms for SKUs w/o HDA audio.
Change-Id: Ice28ea7445a5cb32fe8263ada363d4f45c3152f5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87090
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit introduces a mechanism to allow mainboards to override
the default FSP-M UPDs for Panther Lake.
- Adds `variant_update_soc_memory_init_params` as a weak function
in `variants.h` and `romstage.c` for board-specific implementations.
- In `romstage.c`, `mainboard_memory_init_params` now calls
`variant_update_soc_memory_init_params` to apply board-specific
overrides to the FSP-M UPDs.
This enables finer-grained control over memory initialization parameters
at the variant level.
BUG=b:328770565
TEST=Able to build and boot google/fatcat.
Change-Id: I403bc4270ef526363defa6cd7d22741ad42a8a76
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87089
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: I5643fe19f349facffab218e0e8da02d88f192e73
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: Ifd24ca28d66e5e987129a44b6682efab9b64049b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87103
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
