mb/novacustom/mtl-h: Add discrete graphics variant
Add NovaCustom V540TNx and V560TNx, which are variants of the mtl-h baseboard, but with discrete graphics, compared to the igpu variant. Other notable differences: - 16" models come with TAS5825 Smart Amp - Realtek RTL8111 network adapter - 14" models have only one SSD slot - The non-Thunderbolt USB-C port has DP Alt mode with displayport lanes sourced from the discrete graphics - HDMI port is wired to discrete graphics NVIDIA dGPU ASL code will be added in subsequent patches. TEST=Build V560TNx with UEFIPayload and boot to payload Change-Id: I2b8194c486de1ba3e04aa74ed63caa7a151fbb8b Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This commit is contained in:
Michał Kopeć
Matt DeVillier
parent
cbafdf6d00
commit
66d119480c
14 changed files with 2952 additions and 5 deletions
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@ -23,6 +23,20 @@ config BOARD_NOVACUSTOM_MTLH_COMMON
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select SPD_READ_BY_WORD
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select SYSTEM_TYPE_LAPTOP
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config BOARD_NOVACUSTOM_V5X0TNX_BASE
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bool
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select EC_DASHARO_EC_DGPU
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select BOARD_NOVACUSTOM_MTLH_COMMON
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select DRIVERS_I2C_TAS5825M
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config BOARD_NOVACUSTOM_V540TNX
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bool
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select BOARD_NOVACUSTOM_V5X0TNX_BASE
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config BOARD_NOVACUSTOM_V560TNX
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bool
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select BOARD_NOVACUSTOM_V5X0TNX_BASE
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config BOARD_NOVACUSTOM_V5X0TU_BASE
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bool
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select BOARD_NOVACUSTOM_MTLH_COMMON
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@ -43,15 +57,18 @@ config MAINBOARD_DIR
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config VARIANT_DIR
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default "igpu" if BOARD_NOVACUSTOM_V5X0TU_BASE
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default "dgpu" if BOARD_NOVACUSTOM_V5X0TNX_BASE
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config OVERRIDE_DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
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config MAINBOARD_PART_NUMBER
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default "V54x_6x_TU" if BOARD_NOVACUSTOM_V5X0TU_BASE
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default "V5xTNC_TND_TNE" if BOARD_NOVACUSTOM_V5X0TNX_BASE
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config MAINBOARD_SMBIOS_PRODUCT_NAME
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default "V54x_6x_TU" if BOARD_NOVACUSTOM_V5X0TU_BASE
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default "V5xTNC_TND_TNE" if BOARD_NOVACUSTOM_V5X0TNX_BASE
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config MAINBOARD_SMBIOS_MANUFACTURER
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default "Notebook"
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@ -59,6 +76,8 @@ config MAINBOARD_SMBIOS_MANUFACTURER
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config MAINBOARD_VERSION
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default "V540TU" if BOARD_NOVACUSTOM_V540TU
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default "V560TU" if BOARD_NOVACUSTOM_V560TU
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default "V540TNx" if BOARD_NOVACUSTOM_V540TNX
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default "V560TNx" if BOARD_NOVACUSTOM_V560TNX
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config MAINBOARD_FAMILY
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string
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@ -1,7 +1,13 @@
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comment "Meteor Lake H"
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config BOARD_NOVACUSTOM_V540TNX
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bool "V540TNx (14\", discrete graphics)"
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config BOARD_NOVACUSTOM_V560TNX
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bool "V560TNx (16\", discrete graphics)"
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config BOARD_NOVACUSTOM_V540TU
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bool "V540TU (14\")"
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bool "V540TU (14\", integrated graphics)"
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config BOARD_NOVACUSTOM_V560TU
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bool "V560TU (16\")"
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bool "V560TU (16\", integrated graphics)"
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@ -11,5 +11,6 @@ romstage-y += variants/$(VARIANT_DIR)/gpio.c
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ramstage-y += ramstage.c
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ramstage-y += variants/${VARIANT_DIR}/hda_verb.c
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ramstage-y += variants/$(VARIANT_DIR)/gpio.c
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ramstage-y += variants/$(VARIANT_DIR)/ramstage.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
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@ -12,6 +12,6 @@
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#endif
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void mainboard_configure_early_gpios(void);
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void mainboard_configure_gpios(void);
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void variant_configure_gpios(void);
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#endif
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@ -0,0 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef MAINBOARD_VARIANTS_H
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#define MAINBOARD_VARIANTS_H
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void variant_devtree_update(void);
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#endif
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@ -2,6 +2,7 @@
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#include <ec/dasharo/ec/acpi.h>
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#include <mainboard/gpio.h>
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#include <mainboard/variants.h>
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#include <smbios.h>
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#include <soc/ramstage.h>
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@ -20,9 +21,15 @@ smbios_wakeup_type smbios_system_wakeup_type(void)
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return SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
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}
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void __weak variant_devtree_update(void)
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{
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/* Override dev tree settings per board */
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}
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static void mainboard_init(void *chip_info)
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{
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mainboard_configure_gpios();
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variant_configure_gpios();
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variant_devtree_update();
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}
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struct chip_operations mainboard_ops = {
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BIN
src/mainboard/novacustom/mtl-h/variants/dgpu/data.vbt
Normal file
BIN
src/mainboard/novacustom/mtl-h/variants/dgpu/data.vbt
Normal file
Binary file not shown.
329
src/mainboard/novacustom/mtl-h/variants/dgpu/gpio.c
Normal file
329
src/mainboard/novacustom/mtl-h/variants/dgpu/gpio.c
Normal file
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@ -0,0 +1,329 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <mainboard/gpio.h>
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#include <soc/gpio.h>
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#include <gpio.h>
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#include <timer.h>
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#include <delay.h>
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static const struct pad_config gpio_table[] = {
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/* ------- GPIO Community 0 ------- */
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/* ------- GPIO Group CPU ------- */
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/* ------- GPIO Group V ------- */
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PAD_CFG_NF(GPP_V00, UP_20K, DEEP, NF1), /* BATLOW# */
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PAD_CFG_NF(GPP_V01, NATIVE, DEEP, NF1), /* ACPRESENT */
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PAD_CFG_GPI_TRIG_OWN(GPP_V02, NATIVE, DEEP, OFF, ACPI), /* GPIO - CPU_LAN_WAKEUP# */
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PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1), /* PWRBTN# */
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PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), /* SLP_S3# */
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PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), /* SLP_S4# */
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PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), /* SLP_A# */
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PAD_CFG_GPO(GPP_V07, 0, DEEP), /* GPIO */
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PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), /* SUSCLK */
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PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), /* SLP_WLAN# */
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PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1), /* SLP_S5# */
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PAD_CFG_GPO(GPP_V11, 1, DEEP), /* GPIO - GPIO_LAN_EN */
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PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), /* SLP_LAN# */
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PAD_CFG_GPO(GPP_V13, 0, DEEP), /* GPIO */
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PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), /* WAKE# */
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PAD_CFG_GPO(GPP_V15, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_V16, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_V17, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_V18, 0, DEEP), /* GPIO */
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PAD_CFG_NF(GPP_V19, NONE, DEEP, NF1), /* n/a */
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PAD_CFG_NF(GPP_V20, NONE, DEEP, NF1), /* n/a */
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PAD_CFG_NF(GPP_V21, NONE, DEEP, NF1), /* n/a */
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PAD_CFG_GPO(GPP_V22, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_V23, 0, DEEP), /* GPIO */
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/* ------- GPIO Group GPP_C ------- */
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PAD_CFG_NF(GPP_C00, UP_20K, DEEP, NF1), /* SMBCLK */
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PAD_CFG_NF(GPP_C01, UP_20K, DEEP, NF1), /* SMBDATA */
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PAD_CFG_GPI_TRIG_OWN(GPP_C02, NONE, DEEP, OFF, ACPI), /* GPIO */
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PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1), /* SML0CLK */
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PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1), /* SML0DATA */
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PAD_CFG_GPO(GPP_C05, 0, DEEP), /* GPIO */
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PAD_CFG_NF(GPP_C06, NONE, RSMRST, NF1), /* SML1CLK */
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PAD_CFG_NF(GPP_C07, NONE, RSMRST, NF1), /* SML1DATA */
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PAD_CFG_GPO(GPP_C08, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_C09, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_C10, 0, DEEP), /* GPIO */
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PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), /* SRCCLKREQ2# */
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PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* SRCCLKREQ3# */
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PAD_CFG_GPO(GPP_C13, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_C14, 0, DEEP), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_C15, NONE, DEEP, OFF, ACPI), /* GPIO - CPU_DGPU_PWRGD */
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TBT_LSX0_TXD */
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PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TBT_LSX0_RXD */
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PAD_CFG_GPO(GPP_C18, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_C19, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_C20, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_C21, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_C22, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_C23, 0, DEEP), /* GPIO */
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/* ------- GPIO Community 1 ------- */
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/* ------- GPIO Group GPP_A ------- */
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PAD_CFG_NF(GPP_A00, UP_20K, DEEP, NF1), /* ESPI_IO0 */
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PAD_CFG_NF(GPP_A01, UP_20K, DEEP, NF1), /* ESPI_IO1 */
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PAD_CFG_NF(GPP_A02, UP_20K, DEEP, NF1), /* ESPI_IO2 */
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PAD_CFG_NF(GPP_A03, UP_20K, DEEP, NF1), /* ESPI_IO3 */
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PAD_CFG_NF(GPP_A04, UP_20K, DEEP, NF1), /* ESPI_CS0# */
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PAD_CFG_NF(GPP_A05, UP_20K, DEEP, NF1), /* ESPI_CLK */
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PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1), /* ESPI_RESET# */
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PAD_CFG_GPO(GPP_A07, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_A08, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_A09, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_A10, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_A11, 0, DEEP), /* GPIO - ADDS_CODE */
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PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, DEEP, OFF, ACPI), /* GPIO - WLAN_WAKEUP# */
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PAD_CFG_TERM_GPO(GPP_A13, 1, UP_20K, PLTRST), /* GPIO - M2_SSD2_RST# */
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PAD_CFG_GPI_TRIG_OWN(GPP_A14, UP_20K, DEEP, OFF, ACPI), /* GPIO - NVVDD_ALERT# */
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PAD_CFG_GPO(GPP_A15, 0, DEEP), /* GPIO - CPU_SWI# */
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PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1), /* RSVD - ESPI_ALERT0# */
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PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), /* GPIO - TP_ATTN# */
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PAD_CFG_GPO(GPP_A18, 0, DEEP), /* GPIO - TEST_R (ANX7411) */
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PAD_CFG_GPI_APIC(GPP_A19, NONE, DEEP, LEVEL, NONE), /* GPIO - INTP_OUT (ANX7411) */
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PAD_CFG_GPO(GPP_A20, 1, DEEP), /* GPIO - LAN_PLT_RST# */
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PAD_CFG_NF(GPP_A21, NATIVE, DEEP, NF1), /* PMCALERT# */
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PAD_NC(GPP_A22, NATIVE), /* GPIO */
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PAD_NC(GPP_A23, NATIVE), /* GPIO */
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/* ------- GPIO Group GPP_E ------- */
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PAD_CFG_GPI_TRIG_OWN(GPP_E00, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID7 */
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PAD_CFG_GPI_APIC(GPP_E01, UP_20K, DEEP, LEVEL, NONE), /* GPIO - TPM_PIRQ# */
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PAD_CFG_GPI_TRIG_OWN(GPP_E02, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID4 */
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PAD_CFG_GPI_TRIG_OWN(GPP_E03, NONE, DEEP, OFF, ACPI), /* GPIO - CPU_CNVI_WAKE# */
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PAD_CFG_GPO(GPP_E04, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_E05, 0, DEEP), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, DEEP, OFF, ACPI), /* GPIO */
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PAD_CFG_GPO(GPP_E07, 0, DEEP), /* GPIO - CPU_SMI# */
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PAD_CFG_GPO(GPP_E08, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_E09, 1, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_E10, 0, DEEP), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_E11, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID6 */
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PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8), /* I2C4_SDA - ANX7411 */
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PAD_CFG_NF(GPP_E13, NONE, DEEP, NF8), /* I2C4_SCL - ANX7411 */
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PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDSP_HPDA */
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PAD_CFG_GPO(GPP_E15, 0, DEEP), /* GPIO - CPU_SCI# */
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PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2), /* VRALERT# */
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PAD_CFG_GPI_TRIG_OWN(GPP_E17, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID5 */
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PAD_CFG_GPO(GPP_E18, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_E19, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_E20, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_E21, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_E22, 0, DEEP), /* GPIO */
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PAD_NC(GPP_E23, NONE), /* GPIO */
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PAD_NC(GPP_THC0_GSPI_CLK_LPBK, NONE), /* GPIO */
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/* ------- GPIO Community 3 ------- */
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/* ------- GPIO Group GPP_H ------- */
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PAD_CFG_GPO(GPP_H00, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_H01, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_H02, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_H03, 0, DEEP), /* GPIO */
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PAD_CFG_NF(GPP_H04, NONE, DEEP, NF2), /* CNV_MFUART2_RXD */
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PAD_CFG_NF(GPP_H05, NONE, DEEP, NF2), /* CNV_MFUART2_TXD */
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PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), /* I2C3_SDA */
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PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), /* I2C3_SCL */
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PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), /* UART0_RXD */
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PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), /* UART0_TXD */
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PAD_CFG_GPO(GPP_H10, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_H11, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_H12, 0, DEEP), /* GPIO */
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PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), /* PROC_C10_GATE# */
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PAD_CFG_GPO(GPP_H14, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_H15, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_H16, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_H17, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_H18, 0, DEEP), /* GPIO */
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PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), /* I2C0_SDA */
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PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), /* I2C0_SCL */
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PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), /* I2C1_SDA */
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PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), /* I2C1_SCL */
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PAD_NC(GPP_H23, NONE), /* GPIO */
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PAD_NC(GPP_LPI3C1_CLK_LPBK, NATIVE), /* GPIO */
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PAD_CFG_NF(GPP_LPI3C0_CLK_LPBK, NATIVE, DEEP, NF2), /* n/a */
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/* ------- GPIO Group GPP_F ------- */
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PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), /* CNV_BRI_DT */
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PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1), /* CNV_BRI_RSP */
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PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), /* CNV_RGI_DT */
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PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1), /* CNV_RGI_RSP */
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PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), /* CNV_RF_RESET# */
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PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), /* MODEM_CLKREQ */
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PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1), /* CNVI_GNSS_PA_BLANKING */
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PAD_CFG_GPO(GPP_F07, 0, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_F08, 0, DEEP), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_F09, NONE, DEEP, OFF, ACPI), /* GPIO - TPM_DET */
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PAD_CFG_GPO(GPP_F10, 0, DEEP), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID3 */
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PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8), /* I2C5_SCL - Smart AMP */
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PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), /* I2C5_SDA - Smart AMP */
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PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID1 */
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PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID2 */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_F16, NONE, DEEP, OFF, ACPI), /* GPIO - GPIO4_GC6_NVVDD_EN */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_F17, NONE, PLTRST, OFF, ACPI), /* GPIO - CPU_GC6_FB_EN */
|
||||
PAD_CFG_GPO(GPP_F18, 0, DEEP), /* GPIO -CCD_WP# */
|
||||
PAD_CFG_GPO(GPP_F19, 0, DEEP), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_F20, 0, DEEP), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_F21, 0, DEEP), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_F22, 0, DEEP), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_F23, 0, DEEP), /* GPIO */
|
||||
PAD_NC(GPP_THC1_GSPI1_CLK_LPBK, NONE), /* GPIO */
|
||||
PAD_NC(GPP_GSPI0A_CLK_LOOPBK, NONE), /* GPIO */
|
||||
|
||||
/* ------- GPIO Group SPI ------- */
|
||||
|
||||
/* ------- GPIO Group VGPIO3 ------- */
|
||||
PAD_CFG_NF(GPP_VGPIO3_USB0, NONE, DEEP, NF1), /* GPP_VGPIO3_USB0 */
|
||||
PAD_CFG_NF(GPP_VGPIO3_USB1, NONE, DEEP, NF1), /* GPP_VGPIO3_USB1 */
|
||||
PAD_CFG_NF(GPP_VGPIO3_USB2, NONE, DEEP, NF1), /* GPP_VGPIO3_USB2 */
|
||||
PAD_CFG_NF(GPP_VGPIO3_USB3, NONE, DEEP, NF1), /* GPP_VGPIO3_USB3 */
|
||||
PAD_CFG_NF(GPP_VGPIO3_USB4, NONE, DEEP, NF1), /* GPP_VGPIO3_USB4 */
|
||||
PAD_CFG_NF(GPP_VGPIO3_USB5, NONE, DEEP, NF1), /* GPP_VGPIO3_USB5 */
|
||||
PAD_CFG_NF(GPP_VGPIO3_USB6, NONE, DEEP, NF1), /* GPP_VGPIO3_USB6 */
|
||||
PAD_CFG_NF(GPP_VGPIO3_USB7, NONE, DEEP, NF1), /* GPP_VGPIO3_USB7 */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_TS0, NONE, DEEP, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_TS1, NONE, DEEP, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC0, NONE, DEEP, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC1, NONE, DEEP, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC2, NONE, DEEP, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC3, NONE, DEEP, OFF, ACPI), /* GPIO */
|
||||
|
||||
/* ------- GPIO Community 4 ------- */
|
||||
|
||||
/* ------- GPIO Group GPP_S ------- */
|
||||
PAD_CFG_GPO(GPP_S00, 0, DEEP), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_S01, 0, DEEP), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_S02, 0, DEEP), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_S03, 0, DEEP), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_S04, 0, DEEP), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_S05, 0, DEEP), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_S06, 0, DEEP), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_S07, 0, DEEP), /* GPIO */
|
||||
|
||||
/* ------- GPIO Group JTAG ------- */
|
||||
|
||||
/* ------- GPIO Community 5 ------- */
|
||||
|
||||
/* ------- GPIO Group GPP_B ------- */
|
||||
PAD_CFG_GPO(GPP_B00, 0, DEEP), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_B01, 0, DEEP), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_B02, 0, DEEP), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_B03, 0, DEEP), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_B04, 0, DEEP), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_B05, 0, DEEP), /* GPIO - CPU_KBCRST# */
|
||||
PAD_CFG_GPO(GPP_B06, 0, DEEP), /* GPIO - ROM_I2C_EN */
|
||||
PAD_CFG_GPO(GPP_B07, 0, DEEP), /* GPIO - PANTONE_WP# */
|
||||
PAD_CFG_GPO(GPP_B08, 0, DEEP), /* GPIO - PS8461_SW (DDS for eDP) */
|
||||
PAD_CFG_GPO(GPP_B09, 0, DEEP), /* GPIO - DGPU_RST#_PCH */
|
||||
PAD_CFG_GPI_SCI(GPP_B10, NONE, PLTRST, EDGE_BOTH, INVERT), /* GPIO - NV Type-C DP HPD */
|
||||
PAD_CFG_GPI_SCI(GPP_B11, NONE, PLTRST, EDGE_BOTH, INVERT), /* GPIO - NV HDMI HPD */
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_S0# */
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLTRST# */
|
||||
PAD_CFG_GPO(GPP_B14, 0, DEEP), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, DEEP, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_B16, 0, DEEP), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_B17, 1, DEEP), /* GPIO - CPU_GPIO_LANRTD3 */
|
||||
PAD_CFG_GPO(GPP_B18, 1, DEEP), /* GPIO - PCH_BT_EN */
|
||||
PAD_CFG_GPO(GPP_B19, 1, DEEP), /* GPIO - WIFI_RF_EN */
|
||||
PAD_CFG_GPO(GPP_B20, 0, DEEP), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_B21, 0, PLTRST), /* GPIO - TBT_FORCE_PWR */
|
||||
PAD_CFG_GPO(GPP_B22, 0, DEEP), /* GPIO */
|
||||
PAD_CFG_TERM_GPO(GPP_B23, 0, DN_20K, DEEP), /* GPIO */
|
||||
PAD_CFG_NF(GPP_ACI3C0_CLK_LPBK, NATIVE, DEEP, NF4), /* n/a */
|
||||
|
||||
/* ------- GPIO Group GPP_D ------- */
|
||||
PAD_CFG_GPO(GPP_D00, 1, DEEP), /* GPIO - SB_BLON */
|
||||
PAD_CFG_GPO(GPP_D01, 1, DEEP), /* GPIO - SSD2_PWR_EN */
|
||||
PAD_CFG_GPO(GPP_D02, 1, DEEP), /* GPIO - M2_SSD1_RST# */
|
||||
PAD_CFG_GPO(GPP_D03, 0, DEEP), /* GPIO - CPU_DGPU_PWR_EN */
|
||||
PAD_CFG_GPO(GPP_D04, 0, DEEP), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_D05, 1, DEEP), /* GPIO - SSD1_PWR_EN */
|
||||
PAD_CFG_GPO(GPP_D06, 0, DEEP), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_D07, 0, DEEP), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_D08, 0, DEEP), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_D09, 0, DEEP), /* GPIO */
|
||||
PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), /* HDA_BCLK */
|
||||
PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1), /* HDA_SYNC */
|
||||
PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), /* HDA_SDO */
|
||||
PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), /* HDA_SDI0 */
|
||||
PAD_CFG_GPO(GPP_D14, 0, DEEP), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_D15, 0, DEEP), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_D16, 0, DEEP), /* GPIO - GPIO_SPK_MUTE */
|
||||
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* HDA_RST# */
|
||||
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* SRCCLKREQ6# */
|
||||
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* SRCCLKREQ7# */
|
||||
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* SRCCLKREQ8# */
|
||||
PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2), /* SRCCLKREQ5# */
|
||||
PAD_CFG_NF(GPP_D22, NATIVE, DEEP, NF1), /* n/a */
|
||||
PAD_CFG_NF(GPP_D23, NATIVE, DEEP, NF1), /* n/a */
|
||||
PAD_CFG_NF(GPP_BOOTHALT_B, UP_20K, DEEP, NF1), /* GPP_BOOTHALT_B */
|
||||
|
||||
/* ------- GPIO Group VGPIO ------- */
|
||||
PAD_CFG_GPO(GPP_VGPIO00, 1, DEEP), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO04, NONE, DEEP, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_VGPIO05, 1, DEEP), /* GPIO */
|
||||
PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO06, 0, NONE, DEEP, LEVEL, ACPI), /* GPIO */
|
||||
PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO07, 0, NONE, DEEP, LEVEL, ACPI), /* GPIO */
|
||||
PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO08, 0, NONE, DEEP, LEVEL, ACPI), /* GPIO */
|
||||
PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO09, 0, NONE, DEEP, LEVEL, ACPI), /* GPIO */
|
||||
PAD_CFG_NF(GPP_VGPIO10, NONE, DEEP, NF1), /* GPP_VGPIO10 */
|
||||
PAD_CFG_NF(GPP_VGPIO11, NONE, DEEP, NF1), /* GPP_VGPIO11 */
|
||||
PAD_CFG_NF(GPP_VGPIO12, NONE, DEEP, NF1), /* GPP_VGPIO12 */
|
||||
PAD_CFG_NF(GPP_VGPIO13, NONE, DEEP, NF1), /* GPP_VGPIO13 */
|
||||
PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO18, 0, NONE, DEEP, LEVEL, ACPI), /* GPIO */
|
||||
PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO19, 0, NONE, DEEP, LEVEL, ACPI), /* GPIO */
|
||||
PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO20, 0, NONE, DEEP, LEVEL, ACPI), /* GPIO */
|
||||
PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO21, 0, NONE, DEEP, LEVEL, ACPI), /* GPIO */
|
||||
PAD_CFG_NF(GPP_VGPIO22, NONE, DEEP, NF1), /* GPP_VGPIO22 */
|
||||
PAD_CFG_NF(GPP_VGPIO23, NONE, DEEP, NF1), /* GPP_VGPIO23 */
|
||||
PAD_CFG_NF(GPP_VGPIO24, NONE, DEEP, NF1), /* GPP_VGPIO24 */
|
||||
PAD_CFG_NF(GPP_VGPIO25, NONE, DEEP, NF1), /* GPP_VGPIO25 */
|
||||
PAD_CFG_NF(GPP_VGPIO30, NONE, DEEP, NF3), /* RESERVED */
|
||||
PAD_CFG_NF(GPP_VGPIO31, NONE, DEEP, NF3), /* RESERVED */
|
||||
PAD_CFG_NF(GPP_VGPIO32, NONE, DEEP, NF3), /* RESERVED */
|
||||
PAD_CFG_NF(GPP_VGPIO33, NONE, DEEP, NF3), /* RESERVED */
|
||||
PAD_CFG_NF(GPP_VGPIO34, NONE, DEEP, NF1), /* GPP_VGPIO34 */
|
||||
PAD_CFG_NF(GPP_VGPIO35, NONE, DEEP, NF1), /* GPP_VGPIO35 */
|
||||
PAD_CFG_NF(GPP_VGPIO36, NONE, DEEP, NF1), /* GPP_VGPIO36 */
|
||||
PAD_CFG_NF(GPP_VGPIO37, NONE, DEEP, NF1), /* GPP_VGPIO37 */
|
||||
PAD_CFG_NF(GPP_VGPIO40, NONE, DEEP, NF2), /* RESERVED */
|
||||
PAD_CFG_NF(GPP_VGPIO41, NONE, DEEP, NF2), /* RESERVED */
|
||||
PAD_CFG_NF(GPP_VGPIO42, NONE, DEEP, NF2), /* RESERVED */
|
||||
PAD_CFG_NF(GPP_VGPIO43, NONE, DEEP, NF2), /* RESERVED */
|
||||
PAD_CFG_NF(GPP_VGPIO44, NONE, DEEP, NF1), /* GPP_VGPIO44 */
|
||||
PAD_CFG_NF(GPP_VGPIO45, NONE, DEEP, NF1), /* GPP_VGPIO45 */
|
||||
PAD_CFG_NF(GPP_VGPIO46, NONE, DEEP, NF1), /* GPP_VGPIO46 */
|
||||
PAD_CFG_NF(GPP_VGPIO47, NONE, DEEP, NF1), /* GPP_VGPIO47 */
|
||||
};
|
||||
|
||||
#define DGPU_RST_N GPP_B09
|
||||
#define DGPU_PWR_EN GPP_D03
|
||||
#define DGPU_PWRGD GPP_C15
|
||||
|
||||
/* Pad configuration was generated automatically using intelp2m utility */
|
||||
void variant_configure_gpios(void)
|
||||
{
|
||||
bool result;
|
||||
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
|
||||
/* dGPU power on sequence */
|
||||
mdelay(4);
|
||||
gpio_set(DGPU_PWR_EN, 1);
|
||||
result = wait_ms(200, gpio_get(DGPU_PWRGD) == 1);
|
||||
if (result) {
|
||||
printk(BIOS_INFO, "dGPU powered on\n");
|
||||
gpio_set(DGPU_RST_N, 1);
|
||||
} else {
|
||||
printk(BIOS_ERR, "dGPU failed to power on, turning off\n");
|
||||
gpio_set(DGPU_PWR_EN, 0);
|
||||
}
|
||||
mdelay(50);
|
||||
}
|
||||
87
src/mainboard/novacustom/mtl-h/variants/dgpu/hda_verb.c
Normal file
87
src/mainboard/novacustom/mtl-h/variants/dgpu/hda_verb.c
Normal file
|
|
@ -0,0 +1,87 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/azalia_device.h>
|
||||
#include <gpio.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC245 */
|
||||
0x10ec0245, /* Vendor ID */
|
||||
0x1558a741, /* Subsystem ID */
|
||||
30, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x1558a741),
|
||||
AZALIA_RESET(1),
|
||||
|
||||
0x1271C30, 0x1271D01, 0x1271EA6, 0x1271F90,
|
||||
0x1371C00, 0x1371D00, 0x1371E00, 0x1371F40,
|
||||
0x1871CF0, 0x1871D11, 0x1871E11, 0x1871F41,
|
||||
0x1971CF0, 0x1971D11, 0x1971E11, 0x1971F41,
|
||||
0x1A71CF0, 0x1A71D11, 0x1A71E11, 0x1A71F41,
|
||||
0x1B71CF0, 0x1B71D11, 0x1B71E11, 0x1B71F41,
|
||||
0x1D71C2D, 0x1D71D9B, 0x1D71E68, 0x1D71F40,
|
||||
0x1E71CF0, 0x1E71D11, 0x1E71E11, 0x1E71F41,
|
||||
0x2171C20, 0x2171D10, 0x2171E21, 0x2171F04,
|
||||
0x5B50006, 0x5B40011, 0x205001A, 0x204810B,
|
||||
0x205004A, 0x2042010, 0x2050038, 0x2044909,
|
||||
0x5C50000, 0x5C43D82, 0x5C50000, 0x5C43D82,
|
||||
0x5350000, 0x534201A, 0x5350000, 0x534201A,
|
||||
0x535001D, 0x5340800, 0x535001E, 0x5340800,
|
||||
0x5350003, 0x5341EC4, 0x5350004, 0x5340000,
|
||||
0x5450000, 0x5442000, 0x545001D, 0x5440800,
|
||||
0x545001E, 0x5440800, 0x5450003, 0x5441EC4,
|
||||
0x5450004, 0x5440000, 0x5350000, 0x534A01A,
|
||||
0x205003C, 0x204F175, 0x205003C, 0x204F135,
|
||||
0x2050040, 0x2048800, 0x5A50001, 0x5A4001F,
|
||||
0x2050010, 0x2040020, 0x2050010, 0x2040020,
|
||||
0x170500, 0x170500, 0x5A50004, 0x5A40113,
|
||||
0x2050008, 0x2046A8C, 0x2050076, 0x204F000,
|
||||
0x205000E, 0x20465C0, 0x2050033, 0x2048580,
|
||||
0x2050069, 0x204FDA8, 0x2050068, 0x2040000,
|
||||
0x2050003, 0x2040002, 0x2050069, 0x2040000,
|
||||
0x2050068, 0x2040001, 0x205002E, 0x204290E,
|
||||
0x2050010, 0x2040020, 0x2050010, 0x2040020,
|
||||
|
||||
/* Intel Meteor Lake HDMI */
|
||||
0x8086281d, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
10, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x04, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x08, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
||||
static const u32 smartamp_verbs[] = {
|
||||
0x1471CF0, 0x1471D11, 0x1471E11, 0x1471F41,
|
||||
0x1771C10, 0x1771D01, 0x1771E17, 0x1771F90,
|
||||
};
|
||||
|
||||
static const u32 no_smartamp_verbs[] = {
|
||||
0x1471C10, 0x1471D01, 0x1471E17, 0x1471F90,
|
||||
0x1771C11, 0x1771D01, 0x1771E17, 0x1771F90,
|
||||
0x205006B, 0x204A390, 0x205006B, 0x204A390,
|
||||
0x205006C, 0x2040C9E, 0x205006D, 0x2040C00,
|
||||
};
|
||||
|
||||
void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid)
|
||||
{
|
||||
if (gpio_get(GPP_E00)) {
|
||||
printk(BIOS_INFO, "Normal amp detected\n");
|
||||
azalia_program_verb_table(base, no_smartamp_verbs,
|
||||
ARRAY_SIZE(no_smartamp_verbs));
|
||||
} else {
|
||||
printk(BIOS_INFO, "Smart amp detected\n");
|
||||
azalia_program_verb_table(base, smartamp_verbs,
|
||||
ARRAY_SIZE(smartamp_verbs));
|
||||
}
|
||||
}
|
||||
75
src/mainboard/novacustom/mtl-h/variants/dgpu/overridetree.cb
Normal file
75
src/mainboard/novacustom/mtl-h/variants/dgpu/overridetree.cb
Normal file
|
|
@ -0,0 +1,75 @@
|
|||
chip soc/intel/meteorlake
|
||||
# Power limits,
|
||||
# PsysPL2, PsysPL3, PL4 are configured by EC at runtime
|
||||
register "power_limits_config[MTL_P_682_482_CORE]" = "{
|
||||
.tdp_pl1_override = 35,
|
||||
.tdp_pl2_override = 64,
|
||||
.tdp_pl4 = 120,
|
||||
.psys_pmax = 180,
|
||||
}"
|
||||
|
||||
# MTL SOC has additional setting for PsysPmax
|
||||
register "psys_pmax_watts" = "180"
|
||||
|
||||
device domain 0 on
|
||||
subsystemid 0x1558 0xa741 inherit
|
||||
device ref pcie_rp12 on # PEG
|
||||
register "pcie_rp[PCH_RP(12)]" = "{
|
||||
.clk_src = 6,
|
||||
.clk_req = 6,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
|
||||
}"
|
||||
device pci 00.0 on
|
||||
subsystemid 0x1558 0xa761
|
||||
end
|
||||
end
|
||||
device ref igpu on
|
||||
register "ddi_port_A_config" = "1"
|
||||
register "ddi_ports_config" = "{
|
||||
[DDI_PORT_A] = DDI_ENABLE_HPD, /* eDP */
|
||||
}"
|
||||
end
|
||||
device ref i2c0 on # Touchpad
|
||||
register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""ELAN0412""
|
||||
register "generic.desc" = ""ELAN Touchpad""
|
||||
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
|
||||
register "generic.detect" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 15 on end
|
||||
end
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""FTCS1000""
|
||||
register "generic.desc" = ""FocalTech Touchpad""
|
||||
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
|
||||
register "generic.detect" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 38 on end
|
||||
end
|
||||
end
|
||||
device ref i2c4 on # ANX7443 USB-C Retimer
|
||||
register "serial_io_i2c_mode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
|
||||
end
|
||||
device ref i2c5 on # TAS5825M SmartAmp
|
||||
register "serial_io_i2c_mode[PchSerialIoIndexI2C5]" = "PchSerialIoPci"
|
||||
chip drivers/i2c/tas5825m
|
||||
register "id" = "0"
|
||||
device i2c 4e on end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp5 on # GLAN
|
||||
register "pcie_rp[PCH_RP(5)]" = "{
|
||||
.clk_src = 2,
|
||||
.clk_req = 2,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_V11)"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A20)"
|
||||
register "srcclk_pin" = "2"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
11
src/mainboard/novacustom/mtl-h/variants/dgpu/ramstage.c
Normal file
11
src/mainboard/novacustom/mtl-h/variants/dgpu/ramstage.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <mainboard/variants.h>
|
||||
#include <gpio.h>
|
||||
|
||||
void variant_devtree_update(void)
|
||||
{
|
||||
struct device *i2c_amp_dev = pcidev_on_root(0x19, 1);
|
||||
if (i2c_amp_dev)
|
||||
i2c_amp_dev->enabled = !gpio_get(GPP_E00);
|
||||
}
|
||||
2396
src/mainboard/novacustom/mtl-h/variants/dgpu/tas5825m.c
Normal file
2396
src/mainboard/novacustom/mtl-h/variants/dgpu/tas5825m.c
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -568,7 +568,7 @@ static const struct pad_config gpio_table[] = {
|
|||
PAD_CFG_NF(GPP_VGPIO47, NONE, DEEP, NF1),
|
||||
};
|
||||
|
||||
void mainboard_configure_gpios(void)
|
||||
void variant_configure_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
|
|
|
|||
8
src/mainboard/novacustom/mtl-h/variants/igpu/ramstage.c
Normal file
8
src/mainboard/novacustom/mtl-h/variants/igpu/ramstage.c
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
/* SPDX-License-Identifier: CC-PDDC */
|
||||
|
||||
/* Please update the license if adding licensable material. */
|
||||
|
||||
/*
|
||||
* This is a placeholder, if there ever is something variant specific to
|
||||
* add to ramstage, do it here.
|
||||
*/
|
||||
Loading…
Add table
Add a link
Reference in a new issue