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mb/starlabs/starbook/mtl: Correct SSD GPIO config

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The SSD uses GPP_A20 for reset, and GPP_H07 for enable. Correct the GPIO
configuration and corresponding entry in the devicetree.

Change-Id: I71196f65883803ba9bfc8228bb74f25795bb3a6c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87127
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sean Rhodes 2025-04-02 20:55:15 +01:00 • committed by Matt DeVillier
commit 470660d44e
2 changed files with 4 additions and 4 deletions
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2
src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
View file

@ -214,7 +214,7 @@ chip soc/intel/meteorlake
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H07)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H00)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A20)"
register "srcclk_pin" = "8"
register "is_storage" = "true"
register "add_acpi_dma_property" = "true"

6
src/mainboard/starlabs/starbook/variants/mtl/gpio.c
View file

@ -45,7 +45,7 @@ const struct pad_config gpio_table[] = {
/* SSD */
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* Clock Request 8 */
PAD_CFG_GPO(GPP_H00, 1, PLTRST), /* Reset */
PAD_CFG_GPO(GPP_A20, 1, PLTRST), /* Reset */
PAD_CFG_GPO(GPP_H07, 1, PLTRST), /* Enable */
/* Wireless */
@ -200,8 +200,6 @@ const struct pad_config gpio_table[] = {
PAD_NC(GPP_A18, NONE),
/* A19: */
PAD_NC(GPP_A19, NONE),
/* A20: M.2_CPU_SSD_RESET_N */
PAD_CFG_GPO(GPP_A20, 1, PLTRST),
/* A22: */
PAD_NC(GPP_A22, NONE),
/* A23: */
@ -260,6 +258,8 @@ const struct pad_config gpio_table[] = {
* Start: GPP_H00
* End: GPP_H23
*/
/* H00: */
PAD_NC(GPP_H00, NONE),
/* H03: */
PAD_NC(GPP_H03, NONE),
/* H04: */