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mb/starlabs/starlite_adl: Disconnect the SML 0 and 1 GPIOs

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These are not connected to anything, so configure them accordingly.

Change-Id: Ia3a528faf74c23d0b78210b22c6e8d3f69de8184
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Sean Rhodes 2025-04-02 14:37:31 +01:00
commit 28f1c5ad80
1 changed files with 4 additions and 8 deletions
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12
src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
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@ -140,14 +140,10 @@ const struct pad_config gpio_table[] = {
PAD_NC(GPP_B24, NONE),
PAD_NC(GPP_B25, NONE),
/* C3: SML 0 Clock */
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
/* C4: SML 0 Data */
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
/* C6: SML 1 Clock */
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
/* C7: SML 1 Data */
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
PAD_NC(GPP_C3, NONE),
PAD_NC(GPP_C4, NONE),
PAD_NC(GPP_C6, NONE),
PAD_NC(GPP_C7, NONE),
PAD_NC(GPP_C8, NONE),
PAD_NC(GPP_C9, NONE),
PAD_NC(GPP_C10, NONE),