mb/google/fatcat: Enable HDA SDI based on FW config

This commit modifies the handling of PCH High Definition Audio (HDA)
Serial Digital Interface (SDI) enablement.

- In `devicetree.cb`, the static `pch_hda_sdi_enable` property is
  removed to allow varaints to override if needed.
- In `variant.c`, `variant_update_soc_memory_init_params` is
  introduced to dynamically configure `PchHdaSdiEnable` UPD based on
  the firmware configuration (for example: `AUDIO_ALC256_HDA` or
  `AUDIO_ALC256M_CG_HDA`).
  SDI is enabled if this FW config option is present. Otherwise, it
  defaults to disabled.
- `variant.c` is now added for romstage as well because the SDI
  configuration needs to happen earlier in the boot process.

BUG=b:328770565, b:407876136
TEST=Able to reduce the boot time by 18ms for SKUs w/o HDA audio.

Change-Id: Ice28ea7445a5cb32fe8263ada363d4f45c3152f5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87090
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Subrata Banik 2025-04-02 18:14:07 +05:30
commit 3a88eb8cb6
5 changed files with 32 additions and 3 deletions

View file

@ -98,7 +98,6 @@ chip soc/intel/pantherlake
register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
register "pch_hda_idisp_codec_enable" = "true"
register "pch_hda_sdi_enable" = "{ true, false }"
device domain 0 on
device ref dtt on end

View file

@ -5,5 +5,5 @@ romstage-y += gpio.c
romstage-y += memory.c
romstage-$(CONFIG_FW_CONFIG) += fw_config.c
ramstage-y += gpio.c
ramstage-$(CONFIG_FW_CONFIG) += variant.c
romstage-$(CONFIG_FW_CONFIG) += variant.c
ramstage-$(CONFIG_FW_CONFIG) += fw_config.c

View file

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <baseboard/variants.h>
#include <fsp/api.h>
#include <fw_config.h>
#include <sar.h>
@ -25,3 +26,15 @@ void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
}
}
}
void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
{
FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
/* HDA Audio */
if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256_HDA))) {
printk(BIOS_INFO, "Overriding HDA SDI lanes.\n");
m_cfg->PchHdaSdiEnable[0] = true;
m_cfg->PchHdaSdiEnable[1] = false;
}
}

View file

@ -5,6 +5,6 @@ bootblock-y += gpio.c
romstage-y += gpio.c
romstage-y += memory.c
romstage-$(CONFIG_FW_CONFIG) += fw_config.c
romstage-$(CONFIG_FW_CONFIG) += variant.c
ramstage-y += gpio.c
ramstage-$(CONFIG_FW_CONFIG) += fw_config.c

View file

@ -0,0 +1,17 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <baseboard/variants.h>
#include <fsp/api.h>
#include <fw_config.h>
void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
{
FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
/* HDA Audio */
if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256M_CG_HDA))) {
printk(BIOS_INFO, "Overriding HDA SDI lanes.\n");
m_cfg->PchHdaSdiEnable[0] = true;
m_cfg->PchHdaSdiEnable[1] = false;
}
}