mb/starlabs/starbook/*: Tidy GPIO comments for PCH
This is a non-functional change, and only makes the GPIOs easier to read. Change-Id: I8dd5fade69b9e1c2b24b8ffaeac7f72e72894b9c Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87111 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
parent
6dd323e159
commit
4290340ae5
9 changed files with 51 additions and 64 deletions
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@ -63,6 +63,13 @@ const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), /* Data Input */
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PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1), /* Reset */
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/* PCH */
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PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* C10 Gate */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* Platform Reset */
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PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* Vendor ID 0 */
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PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* Vendor ID 1 */
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PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT), /* Processor Hot */
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/* GPD2: LAN Wake */
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PAD_NC(GPD2, NONE),
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/* GPD6: Sleep A */
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@ -106,12 +113,6 @@ const struct pad_config gpio_table[] = {
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PAD_NC(GPP_A23, NONE),
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/* B0: Core Vendor ID 0 */
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PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
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/* B1: Core Vendor ID 1 */
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PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
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/* B2: BC PROCHOT */
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PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),
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/* B3: Not Connected */
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PAD_NC(GPP_B3, NONE),
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/* B4: Not Connected */
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@ -132,8 +133,6 @@ const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
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/* B12: PM SLP S0 */
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PAD_NC(GPP_B12, NONE),
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/* B13: PLT RST */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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/* B14: Top Swap Override Weak Internal PD 20K
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High: Enabled
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Low: Disabled */
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@ -365,8 +364,6 @@ const struct pad_config gpio_table[] = {
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PAD_NC(GPP_H14, NONE),
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/* H16: Not Connected */
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PAD_NC(GPP_H16, NONE),
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/* H18: CPI C10 Gate */
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PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
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/* H19: Clock Request 4 */
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PAD_NC(GPP_H19, NONE),
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/* H20: Not Connected */
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@ -64,6 +64,13 @@ const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), /* Data Input */
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PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1), /* Reset */
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/* PCH */
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PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* C10 Gate */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* Platform Reset */
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PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* Vendor ID 0 */
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PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* Vendor ID 1 */
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PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT), /* Processor Hot */
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/* GPD2: LAN Wake */
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PAD_NC(GPD2, NONE),
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/* GPD6: Sleep A */
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@ -106,12 +113,6 @@ const struct pad_config gpio_table[] = {
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/* A23: Not Connected */
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PAD_NC(GPP_A23, NONE),
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/* B0: Core Vendor ID 0 */
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PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
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/* B1: Core Vendor ID 1 */
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PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
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/* B2: BC PROCHOT */
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PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),
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/* B3: Not Connected */
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PAD_NC(GPP_B3, NONE),
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/* B4: Not Connected */
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@ -132,8 +133,6 @@ const struct pad_config gpio_table[] = {
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PAD_NC(GPP_B11, NONE),
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/* B12: PM SLP S0 */
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PAD_NC(GPP_B12, NONE),
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/* B13: PLT RST */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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/* B14: Top Swap Override Weak Internal PD 20K
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High: Enabled
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Low: Disabled */
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@ -367,8 +366,6 @@ const struct pad_config gpio_table[] = {
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PAD_NC(GPP_H14, NONE),
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/* H16: Not Connected */
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PAD_NC(GPP_H16, NONE),
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/* H18: CPI C10 Gate */
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PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
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/* H19: Clock Request 4 CPU M.2 SSD */
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PAD_NC(GPP_H19, NONE),
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/* H20: Not Connected */
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@ -59,6 +59,10 @@ const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* HDMI Data */
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PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* TCP0 Hot Plug */
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/* PCH */
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PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* C10 Gate */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* Platform Reset */
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/* GPD2: LAN_WAKE# */
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PAD_NC(GPD2, NONE),
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/* GPD6: SIO_SLP_A# */
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@ -141,8 +145,6 @@ const struct pad_config gpio_table[] = {
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PAD_CFG_GPO(GPP_B11, 1, PLTRST),
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/* B12: PM_SLP_S0_N */
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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/* B13: PLT_RST_N */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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/* B14: TCH_PNL_PWR_EN */
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PAD_CFG_GPO(GPP_B14, 1, PLTRST),
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/* B15: Not Connected */
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@ -373,8 +375,6 @@ const struct pad_config gpio_table[] = {
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PAD_NC(GPP_H16, NONE),
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/* H17: GPPC_H_17_WWAN_DISABLE_N */
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PAD_CFG_GPO(GPP_H17, 0, DEEP),
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/* H18: GPPC_H_18_CPU_C10 */
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PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
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/* H19: Not Connected */
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PAD_NC(GPP_H19, NONE),
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/* H20: Not Connected */
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@ -44,6 +44,9 @@ const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), /* HDMI Data */
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PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* TCP0 Hot Plug */
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/* PCH */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* Platform Reset */
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/* GPD2: Not Connected */
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PAD_NC(GPD2, NONE),
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/* GPD6: Not Connected */
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@ -126,8 +129,6 @@ const struct pad_config gpio_table[] = {
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PAD_NC(GPP_B11, DN_20K),
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/* GPP_B12 SLP_S0_N */
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PAD_NC(GPP_B12, DN_20K),
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/* GPP_B13: SYS_RESET# */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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/* GPP_B14: HDA_SPKR */
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PAD_NC(GPP_B14, DN_20K),
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/* GPP_B15: Not Connected */
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@ -71,6 +71,11 @@ const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), /* Data Input */
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PAD_CFG_NF(GPP_D17, NATIVE, DEEP, NF1), /* Reset */
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/* PCH */
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PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), /* C10 Gate */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* Platform Reset */
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PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, EDGE_SINGLE, INVERT), /* Processor Hot */
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/* V02: PCIE_WAKE_LAN */
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PAD_NC(GPP_V02, NONE),
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/* V06: GPD_6_SLP_A_N */
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@ -237,8 +242,6 @@ const struct pad_config gpio_table[] = {
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PAD_NC(GPP_E13, NONE),
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/* E15: BOOTHALT_N */
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PAD_CFG_NF(GPP_E15, NONE, DEEP, NF2),
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/* E16: BC_PROCHOT_N */
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PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, EDGE_SINGLE, INVERT),
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/* E17: */
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PAD_NC(GPP_E17, NONE),
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/* E18: */
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@ -278,8 +281,6 @@ const struct pad_config gpio_table[] = {
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PAD_NC(GPP_H11, NONE),
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/* H12: */
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PAD_NC(GPP_H12, NONE),
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/* H13: CPU_C10_GATE_N_R */
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PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
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/* H14: */
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PAD_NC(GPP_H14, NONE),
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/* H15: */
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@ -411,8 +412,6 @@ const struct pad_config gpio_table[] = {
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PAD_NC(GPP_B11, NONE),
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/* B12: */
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PAD_NC(GPP_B12, NONE),
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/* B13: PLT_RST_N */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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/* B14: Top Swap Override
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* HIGH: EMABLED
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* LOW: DISABLED
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@ -66,6 +66,13 @@ const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), /* Data Input */
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PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1), /* Reset */
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/* PCH */
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PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* C10 Gate */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* Platform Reset */
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PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* Vendor ID 0 */
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PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* Vendor ID 1 */
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PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT), /* Processor Hot */
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/* GPD2: LAN Wake */
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PAD_NC(GPD2, NONE),
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/* GPD6: Sleep A */
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@ -111,12 +118,6 @@ const struct pad_config gpio_table[] = {
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/* A23: Not Connected */
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PAD_NC(GPP_A23, NONE),
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/* B0: Core Vendor ID 0 */
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PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
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/* B1: Core Vendor ID 1 */
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PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
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/* B2: BC PROCHOT */
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PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),
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/* B3: Not Connected */
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PAD_NC(GPP_B3, NONE),
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/* B4: Not Connected */
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@ -135,8 +136,6 @@ const struct pad_config gpio_table[] = {
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PAD_NC(GPP_B10, NONE),
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/* B12: PM SLP S0 */
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PAD_NC(GPP_B12, NONE),
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/* B13: PLT RST */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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/* B14: Top Swap Override Weak Internal PD 20K
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High: Enabled
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Low: Disabled */
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@ -368,8 +367,6 @@ const struct pad_config gpio_table[] = {
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PAD_NC(GPP_H14, NONE),
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/* H16: Not Connected */
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PAD_NC(GPP_H16, NONE),
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/* H18: CPI C10 Gate */
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PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
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/* H20: Not Connected */
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PAD_NC(GPP_H20, NONE),
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/* H21: Not Connected */
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@ -58,6 +58,10 @@ const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), /* Data Input */
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PAD_NC(GPP_R4, NONE), /* Reset */
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/* PCH */
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PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* C10 Gate */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* Platform Reset */
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/* GPD2: LAN_WAKE# */
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PAD_NC(GPD2, NONE),
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/* GPD6: SIO_SLP_A# */
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@ -127,8 +131,6 @@ const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
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/* B12: PM_SLP_S0_N */
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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/* B13: PLT_RST_N */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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/* B14: FPS_RST_N */
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PAD_CFG_GPO(GPP_B14, 1, PLTRST),
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/* B15: Not Connected */
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@ -340,8 +342,6 @@ const struct pad_config gpio_table[] = {
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PAD_NC(GPP_H14, NONE),
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/* H15: Not Connected */
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PAD_NC(GPP_H15, NONE),
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/* H18: CPU_C10_GATE_N */
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PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
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/* H19: UART_BT_WAKE_N */
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PAD_NC(GPP_H19, NONE),
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/* H20: Not Connected */
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@ -76,6 +76,13 @@ const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), /* Data Input */
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PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1), /* Reset */
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/* PCH */
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PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* C10 Gate */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* Platform Reset */
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PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* Vendor ID 0 */
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PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* Vendor ID 1 */
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PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT), /* Processor Hot */
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/* GPD2: LAN Wake */
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PAD_NC(GPD2, NONE),
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/* GPD6: Sleep A */
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@ -120,12 +127,6 @@ const struct pad_config gpio_table[] = {
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/* A23: Not Connected */
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PAD_NC(GPP_A23, NONE),
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/* B0: Core Vendor ID 0 */
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PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
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/* B1: Core Vendor ID 1 */
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PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
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/* B2: BC PROCHOT */
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PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),
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/* B3: Not Connected */
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PAD_NC(GPP_B3, NONE),
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/* B4: Not Connected */
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@ -363,8 +364,6 @@ const struct pad_config gpio_table[] = {
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PAD_NC(GPP_H14, NONE),
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/* H16: Not Connected */
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PAD_NC(GPP_H16, NONE),
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/* H18: CPI C10 Gate */
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PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
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/* H19: Clock Request 4 CPU M.2 SSD */
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PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
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/* H20: Not Connected */
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@ -64,6 +64,13 @@ const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), /* Data Input */
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PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1), /* Reset */
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/* PCH */
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PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* C10 Gate */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* Platform Reset */
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PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* Vendor ID 0 */
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PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* Vendor ID 1 */
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PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT), /* Processor Hot */
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/* GPD2: LAN Wake */
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PAD_NC(GPD2, NONE),
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/* GPD6: Sleep A */
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@ -105,12 +112,6 @@ const struct pad_config gpio_table[] = {
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PAD_NC(GPP_A23, NONE),
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/* B0: Core Vendor ID 0 */
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PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
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/* B1: Core Vendor ID 1 */
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PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
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/* B2: BC PROCHOT */
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PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),
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/* B3: Not Connected */
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PAD_NC(GPP_B3, NONE),
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/* B4: Not Connected */
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@ -131,8 +132,6 @@ const struct pad_config gpio_table[] = {
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PAD_NC(GPP_B11, NONE),
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/* B12: PM SLP S0 */
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PAD_NC(GPP_B12, NONE),
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/* B13: PLT RST */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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/* B14: Webcam Privacy LED */
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PAD_NC(GPP_B14, NONE),
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/* B15: Not Connected */
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@ -362,8 +361,6 @@ const struct pad_config gpio_table[] = {
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PAD_NC(GPP_H14, NONE),
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/* H16: Not Connected */
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PAD_NC(GPP_H16, NONE),
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/* H18: CPI C10 Gate */
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||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
/* H19: Clock Request 4 */
|
||||
PAD_NC(GPP_H19, NONE),
|
||||
/* H20: Webcam Clock */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue