The mtk_ddp_ovlsys_start function is updated to take edid and path
as arguments. This allows the function to configure the framebuffer
address and overlay for DISP_PATH_DUAL_MIPI path.
BUG=b:319511268
TEST=cherry pick CB:90504 and manual enable BMP_LOGO related configs.
The logo is drawn in the ramstage.
Change-Id: I60809f7062907617f2af1badcad9f53477911020
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Add an option to lock the regions BOOTBLOCK and COREBOOT, leaving the
regions TOPSWAP and COREBOOT_TS for updates in an Intel Top Swap
redundancy scenario.
This means that the user can now write and choose to boot from the
update regions, selecting the attempt_slot_b CMOS option, and there is
a protected golden copy of the entire firmware, that cannot be
overwritten and can be reverted to by resetting CMOS.
This is part of an ongoing implementation of a redundancy feature
proposed on the mailing list:
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
Change-Id: Ia6dea22c41e2fc778af6ca7049b72c92686ec85f
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Before CPU resume, it is necessary to reinitialize the MTE-related
settings of booker in MCUPM to prevent the loss of booker
configurations after resume.
BUG=b:467186613
TEST=Build pass, Verify S/R OK on Navi and Sapphire.
Change-Id: Ieaf4c2ea0f8a5c372a5dbf4d0f6c44fbd978e6a6
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90546
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Move the xxhash lib to commonlib/bsd folder so that it can be
easily included by tools. Update use of standard headers to
allow compilation on POSIX compatible systems as well.
Use the new xxhash lib in cbfstool over the existing duplicated
xxhash lib residing in lz4/lib.
Change-Id: I21041409d5b734cecf43294dcaf3bf17531dbc15
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89682
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FWTS complains on HPET base not being found in DSDT/SSDT:
Test 3 of 4: Test HPET base in DSDT and/or SSDT.
WARNING: Test 3, Test skipped because HPET Device address was not
found in DSDT/SSDT.
Declare HPET device under LPC device to fix the issue.
TEST=Run FWTS on Gigabyte MZ33-AR1 and see no error in HPET tests.
Change-Id: I68b872291dc93320e7a0b33a79e3336e1372b178
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89924
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on AMD doc #48882 PUB Rev 3.10 [1]. Now, the IVHD type 11h and
40h have a second 64bit EFR value that should be filled with IOMMU MMIO
offset 0x1A0 register value if EFR is supported.
[1] https://docs.amd.com/v/u/en-US/48882_IOMMU
Change-Id: I0da79bed8994671c651328cd7a29d9480a122528
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
non-cacheable
Add support to split the dram_aop memory region into three in order to
map dram_aop_cmd_db as non-cacheable. The purpose of dram_aop_config
is memory region where the aop_devcfg.mbn image is loaded.
Test=1. Build and boot on X1P42100.
2. Dump the MMU table in coreboot ramstage and verify whether the region
is mapped as non-cacheable.
Change-Id: Id73d878b7d343f248a845bd5727c43e22c4c348a
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90521
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support to map AOP CMD-DB region as uncached region in MMU. The
reason for this change is that the CMD-DB region is configured as
read-only region and any write to this region will be treated as
fatal. Mapping it as cacheable can lead to cache-line writebacks,
causing invalid accesses and device crashes.
Test=1. Create an image.serial.bin and ensure it boots on X1P42100.
MMU Table dump from Trace32:
'M:0000000081C60000--0000000081C7FFFF| AM:0000000081C60000--0000000081C7FFFF| s | | 00001000| read/write access exec | yes| inn| non-cacheable | 1| no | \\ramstage\Global\_dram_aop_cmd_db'
Change-Id: I296b505f670f3be28eb998fdac8164a85bf757b0
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90464
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The mipi_cmd_func_t callback for mipi_panel_parse_init_commands()
currently doesn't support passing additional data for storing context.
Therefore user code would need to store any extra data in global
variables. For example, in the upcoming DSI dual channel support for
MediaTek platforms, the callback needs to know whether the MIPI panel
supports dual channel or not. To support that use case, pass an extra
`user_data` argument to mipi_cmd_func_t.
BUG=b:424782827
TEST=util/abuild/abuild -x -t GOOGLE_SAPPHIRE -a
BRANCH=none
Change-Id: Id5d7b168cdcadfe8d8435c29d7e855a535815057
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Define the QCLIB_GA_ENABLE_PD_NEGOTIATION bit in the QcLib global
attributes. This flag signals to QcLib that Power Delivery
negotiation should be performed.
BUG=b:457566143
TEST=Verify different boot modes on Google/Quenbi.
TEST=Verify that PD negotiation is skipped in normal mode.
Change-Id: Ia046f68ebeacaa1c1d9a73c4b957315c9f7b68b6
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90512
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce a weak function qclib_mainboard_override to allow
mainboards to customize QcLib policies or global attributes.
This hook is called from the SoC-specific QcLib initialization
path.
BUG=b:457566143
TEST=Configure QcLib policy for Google/Quenbi.
Change-Id: I0397b7138db260973ea86852cfa9f408e14d195d
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Ensure that existing flags in global_attributes are not overwritten
when enabling UART logging. Using a bitwise OR preserves any
previously set attributes.
BUG=b:457566143
TEST=Verify the QcLib global attributes.
With this CL -
```
[DEBUG] Global Attributes[0x3]..Table Entries Count[8]
```
Change-Id: Iffceb06cb800ba4c9e5c07381745cbed1fb7d550
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90509
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit updates the SSRAM memory layout in memlayout.ld to reserve
space for several new regions.
The following regions are added to the SSRAM section:
- qsee: 100K at 0x14680000
- qdss_usb_trace: 8K at 0x146A6000
- aop_imem: 8K at 0x146A8000
The memory map diagram in the comments is also updated to reflect the
reservation of aop_imem and qdss_usb_trace.
BUG=b:456953373
TEST=Able to build and boot google/quenbih.
Change-Id: I17c2a97d31cdcb81ffdd0c83d8c6d19b9a03a91b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90443
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Relocate the PRERAM_STACK region to a new address to resolve a memory
conflict with the QSEE Trust Zone environment.
Details:
- The previous location of the PRERAM_STACK starting at 0x14680000 in
SSRAM is now reserved for QC QSEE.
- This change moves the 16KB PRERAM_STACK from 0x14680000 (SSRAM) to
the available memory region starting at 0x14850000 in the BSRAM.
BUG=b:456953373
BRANCH=None
TEST=Able to build google/bluey.
Change-Id: Ifa9bc457e28b9ec21aa59c6ab9114993f23b2bc8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Implement the newly introduced PRERAM_STACK and POSTRAM_STACK macros in
the x1p42100 memory layout, addressing the memory constraints on this
SoC.
Changes
- Pre-RAM Stack: The temporary stack used before DRAM is ready is
defined using PRERAM_STACK(0x14680000, 16K) in the SSRAM region,
replacing the old generic STACK definition.
- Post-RAM Stack: The final stack is defined using
POSTRAM_STACK(0x80000000, 16K) at the start of DRAM.
- The POSTRAM_DMA_COHERENT region is shifted up to 0x80004000 to
accommodate the new 16KB post-RAM stack, avoiding memory overlap.
This guarantees a distinct and properly sized stack region for each
stage of the boot process, resolving conflicts with Trust Zone and
ensuring a clean stack transition during the RAM stage.
BUG=b:456953373
BRANCH=None
TEST=Able to build google/bluey.
w/o this patch
```
[SPEW ] stack: top_of_stack address is 0x14684000
```
w/ this patch
```
[SPEW ] stack: top_of_stack address is 0x80004000
```
Change-Id: Iccf3f99aff31a8e44386ea52b2196b49797caa79
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90405
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On the X1P42100 SoC, the System Debug Image (SDI) flow is handled by
the Always-On Processor (AOP), unlike previous architectures (e.g.,
Kodiak) which utilized a dedicated 'QcSDI' image.
Rename the memory region at 0x14699000 from 'qcsdi' to 'aop_sdi' to
accurately reflect ownership by the AOP and to align with the new
chipset architecture. This change clarifies the memory map and serves
as a prerequisite for removing legacy QcSDI artifacts once the
modern SDI flow is fully enabled.
BUG=b:456953373
TEST=Build and boot on google/quenbih target.
Change-Id: Ic5626c06decaadfd459aa21bde4efcfec92e1e47
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90505
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Logs such as "DRAM-K: calibration failed: status = 1" give little
information about the failure reason. Add get_status_string() and use it
to print the return status as a string.
Change-Id: If20282f0de7ba8ce884d0016fe8da1dc93a33ea4
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90484
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Optimize the `sdram_size` function by caching the calculated SDRAM
size in a static variable. This prevents redundant calls to
`mtk_dram_size()` or `mem_chip_info_total_density_bytes()` if the size
has already been determined, improving performance in scenarios where
`sdram_size` is called multiple times.
BUG=none
TEST=emerege-tanjiro coreboot
Change-Id: I0ca0df80ee9cb781a5bb6d55ee28a2c1153be0ad
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90485
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This patch enables MTE (Memory Tagging Extension) for the MediaTek
MT8196 SoC.
During `soc_init`, it calculates the required size and start address for
the MTE tag storage based on the physical DRAM size. It then calls
`booker_mte_init` to initialize the MTE hardware with the calculated
start address.
Later, during memory initialization, `bootmem_platform_add_ranges` uses
`bootmem_add_range_from` to reserve the calculated memory region for
MTE tag storage, preventing it from being used for other purposes.
BUG=b:438666196
TEST=Check cbmem log.
[DEBUG] booker_mte_init: MTE tag addr 0x460f70000
...
[DEBUG] 17. 0000000460f70000-000000047ffeffff: TAG STORAGE
[DEBUG] 18. 000000047fff0000-000000047fffffff: RESERVED
Change-Id: I7caa4fde4f314261383a68e942b0e3fb06c6184b
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90144
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
GCC generates correct code for __builtin_bswapXX() on all architectures,
including ArmV4. It seems that whatever bug caused this to not work back
in commit 879ea7fce8 ("endian: Replace explicit byte swapping with
compiler builtin") has been fixed now. We can eliminate the swabXX()
functions and simplify the code.
All instances that had been calling these functions directly should have
been using real endianness conversions anyway.
Change-Id: I19713fd009aa5c0e01c4a42e0cf012364d6bed60
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90438
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
In preparation for the upcoming DSI dual channel support, pass dsi_regs
and mipi_tx_regs to DSI functions that need to access these registers.
BUG=b:424782827
TEST=util/abuild/abuild -x -t GOOGLE_SAPPHIRE -a
BRANCH=none
Change-Id: Ia0c9051148e38a7703119f800d417f2f8b52f78a
Signed-off-by: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90446
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add dsi_register_v3.h to define dsi_regs struct for mt8196, and add
dsi_reg.h to define mipi_tx_regs struct. Unlike other SoCs, mt8196
has dsi1 and mipi_tx1 registers in order to support DSI dual channel.
BUG=b:424782827
TEST=util/abuild/abuild -x -t GOOGLE_SAPPHIRE -a
BRANCH=none
Change-Id: I2b541c89a007f380de482bffa86aca60c351b526
Signed-off-by: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90451
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Move dsi0 variable definition to dsi_register_v*.h to be closer to the
register struct definition. This also allows us to define dsi1 for
mt8196 at the same place as dsi0 in a future patch. The dsi1 variable
cannot be defined in dsi_common.h because not all MediaTek SoCs using
the header have the DSI1_BASE register.
BUG=b:424782827
TEST=util/abuild/abuild -x -t GOOGLE_SAPPHIRE -a
BRANCH=none
Change-Id: I643f8d0317d0fb8bd8ea7bf8870ec99051c35c1b
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90452
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The soc/dsi.h header contains SoC-specific dsi and mipi_tx register
definitions, which are not needed for SoCs not supporting MIPI DSI
panels (such as mt8195). To decouple the generic display.c (used for
both eDP and MIPI panels) from those register definitions, move the
mtk_dsi_init() declaration and MIPI_DSI_* enums to display_dsi.h.
This allows us to remove the unused soc/dsi.h for mt8195.
BUG=b:424782827
TEST=util/abuild/abuild -x -t GOOGLE_ASURADA -a
TEST=emerge-skywalker coreboot
BRANCH=none
Change-Id: I56e458ec8077ed48929637b9b5c70f08653cc73f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90449
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In an upcoming change, a dsi_regs/mipi_tx_regs argument will be added to
functions declared in dsi_common.h. Currently those structs are all
defined in soc/dsi.h. However, dsi_common.h cannot include soc/dsi.h
because soc/dsi.h already includes dsi_common.h. To solve the circular
dependency issue, move the dsi_regs/mipi_tx_regs definitions to a new
file soc/dsi_reg.h.
As mt8183/mt8186/mt8188/mt8189/mt8192 all share compatible mipi_tx_regs
definitions, create a common mipi_tx_reg_v1.h and include it in these
SoCs' soc/mipi_tx_reg.h. The mt8173 remains its own struct definition.
Also, rename MIPITX_BASE to MIPITX0_BASE in soc/addressmap.h, to have
consistent naming across all SoCs. Note that MIPITX1_BASE will be added
for mt8196 in a future patch.
BUG=b:424782827
TEST=emerge-skywalker coreboot
BRANCH=none
Change-Id: I0e2159fde5bfc358691a4b3bdebc2657f0a598a8
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90445
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The address of mipi_tx1 should be MIPI_TX1_BASE instead of
MIPI_TX0_BASE. This doesn't cause any issue in practice because mipi_tx1
is unused.
Also rename lvds_tx1/lvds_tx2 to lvds_tx0/lvds_tx1 for consistency with
the MIPI_TX0_BASE/MIPI_TX1_BASE naming.
BUG=none
TEST=none
BRANCH=none
Change-Id: I040b0a2a447333141cf6f4a012fa5d2aefd936c7
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90444
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
CFR options are added for the following options:
- legacy_8254_timer
- s0ix_enable
- vtd
TEST=build/boot google/reef with CFR support
Change-Id: Ia58bf53f93742417c2aac683c96f7c8f382a35c0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Correct "APCI" to "ACPI" in the UI help text.
Change-Id: I56343c82b2ddc73e565501f723538fbe96877cd6
Signed-off-by: Integral <integral@member.fsf.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90431
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TF-A feature additions have increased BL31 memory requirements. Expand
BL31 reservation from 600KB to 800KB and adjust the TA region start
address to prevent overlap. The TA region change requires FDT memory
reservation updates, which are handled in Depthcharge.This update
ensures proper memory alignment for secure firmware execution.
TEST=Created image.serial.bin and verified successful boot on X1P42100.
Basic device boot functionality with the updated memory reservation has
been validated.
Change-Id: Ia0145c9e8d5925de4a7fee3399efc76059944c10
Signed-off-by: Kirubakaran E <kirue@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
AMD systems have a TOM2WB bit in SYS_CFG MSR to forcefully cover the
address space between 4GB-TOM2 as WB. Any WB MTRR that falls into that
range may be skipped from programming. It can save a lot of MTRRs when
calculating the MTRR solution. It is especially needed when using a
temporary MTRR to cover the flash as WP, as the MTRR space gets more
fragmented.
Add checks for SYS_CFG TOM2WB in the MTRR driver and skip the WB MTRR
ranges when possible.
TEST=Successfully enable temporary MTRR range for flash on Gigabyte
MZ33-AR1.
Change-Id: Ie9af9b54a1037c843d8f019506af761a8d8769d0
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89199
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
clock enablement
Add register address and clock value definitions required to enable
the display clock. The register details are part of HRD-X1P42100-S1
document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
TEST=Generated image.serial.bin and verified boot on X1P42100.
Validated only basic device boot functionality, as clock enablement API
and its invocation sequence from display driver are not yet implemented.
Change-Id: Id23dd12c9c1ee4968546c8b928f9360163446a9d
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
send_global_reset() now returns cse_tx_rx_status, and skips the
CF9 reset only when CSE reports CSE_TX_RX_SUCCESS.
Test=Disable and enable the Intel ME on labtop_kbl and verify the
system actually resets, rather than hanging.
Change-Id: I5003ea9486a383ee7a4cace20ce6a54b0f94a166
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90274
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
cse_request_global_reset() returns CSE_TX_RX_SUCCESS on success. Make
do_global_reset() explicatly check for that, and fall back CF9 for any
other value.
Test=Disable and enable the Intel ME on starbook_mtl and verify the
system actually resets, rather than hanging.
Change-Id: I4c3fb7995bca8e7fe3793b9aee021e4004ace933
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Currently, cse_request_reset() returns 0 if the reset type is
unsupported or CSE isn’t ready. This is the same as
CSE_TX_RX_SUCCESS, which makes failures impossible to detect.
Return CSE_TX_ERR_INPUT or CSE_TX_ERR_CSE_NOT_READY respectively,
so we can detect errors.
Change-Id: Idede7342157901946ba62ba6fcda6f304a4a3fd0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90272
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Fix the bit definition for RGS_AUX_LDO_EN_READY_MASK in the MT8189
dptx_reg.h file, changing it from BIT(2) to BIT(0). The MT8189 is only
polling BIT(0) status instead of BIT(2). This correction ensures proper
functionality of the AUX LDO readiness check.
BUG=b:461384417
TEST=Boot up can see develop mode.
BRANCH=skywalker
Signed-off-by: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Change-Id: Id4a85c619311fecde5bc84ad29c521b7d20ffdd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90362
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use is_dev_enabled() on devicetree device to enable/disable USB4 devices
by updating the corresponding FSP UPDs.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: If0ae88eaaf88954159b55fdf030eb96d74ee29f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Glinda and Faegan are closely related and there's only very minimal
difference from the coreboot viewpoint, so Feagan is added as Glianda
variant and not as a new SoC folder. Faegan has a different CPUID, so
it's added to the CPU table, and some GPIO muxes have a few more valid
settings to route the MDIO pins related to the 2 XGBE controllers to
GPIO pins.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I57699089a4a3ac7ddb037f254d42cb043b816c55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90417
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some specific Glinda SoCs support dual 10G PCI ethernet devices.
Add defines and chipset entries for XGBE0 and XGBE1.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7e3bb1819165a7c2f4284b76450f831bb99b1ad3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90416
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Glinda actually supports warm reset, so we don't need to toggle the
PwrGood for all resets.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I70e9a13b84219847795e65b39c52114592a2cb61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90415
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fill in the DIMM voltages as reported by FSP.
Change-Id: I22d6bac93d8e8b8130f89a440be661829c700fe9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
There is ESPI1 fixed resource living 64K above the ESPI0 fixed
resource. Report it if the hardware has ESPI1 bus.
Change-Id: I7245850450cfa9de326f26c83c4f01c8d167f8be
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
On systems with AMD ROM armor enabled the SPI base address register
in LPC bridge PCI device space is not accessible (returns all FFs).
In such case the AML code will not be able to retrieve the SPI BAR
and report it properly. Use fixed bases instead to avoid running
into this problem in the future.
Change-Id: Ia01508e5ddf2da053f9bf4116c5e05b89500f772
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89488
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the dsc_config parameter to mtk_ddp_soc_mode_set to support DSC
configuration, and updated function calls to pass dsc_config from
panel_serializable_data. The MIPI_DSI_DUAL_CHANNEL flag is set when the
panel uses the dual MIPI path. This patch is prepared for upcoming MIPI
DSI and DSC changes.
BUG=b:424782827
TEST=Build pass.
Change-Id: Ia3ada4aca41a231adb2273c34deef636889c5c81
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90377
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Refactor the MIPI DPHY implementation to improve modularity and
maintainability:
- Extract the dphy timing calculation to mtk_mipi_dphy_v1.c.
- Update Makefiles for multiple chips to include the new file.
- Enhance board-specific tuning by isolating timing configuration logic.
BUG=b:424782827
TEST=Build pass, boot ok, display ok
Change-Id: Ie0daa6e7b384a172ed483eda926e5acd1e3c539a
Signed-off-by: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90358
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
