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soc/mediatek: Move mtk_dsi_init declaration to display_dsi.h

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The soc/dsi.h header contains SoC-specific dsi and mipi_tx register
definitions, which are not needed for SoCs not supporting MIPI DSI
panels (such as mt8195). To decouple the generic display.c (used for
both eDP and MIPI panels) from those register definitions, move the
mtk_dsi_init() declaration and MIPI_DSI_* enums to display_dsi.h.

This allows us to remove the unused soc/dsi.h for mt8195.

BUG=b:424782827
TEST=util/abuild/abuild -x -t GOOGLE_ASURADA -a
TEST=emerge-skywalker coreboot
BRANCH=none

Change-Id: I56e458ec8077ed48929637b9b5c70f08653cc73f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90449
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Yu-Ping Wu 2025-12-10 23:53:25 +08:00 • committed by Yu-Ping Wu
commit 3607024944
5 changed files with 60 additions and 55 deletions
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2
src/soc/mediatek/common/display.c
View file

@ -9,8 +9,8 @@
#include <framebuffer_info.h>
#include <soc/ddp.h>
#include <soc/display.h>
#include <soc/display_dsi.h>
#include <soc/dptx.h>
#include <soc/dsi.h>
#include <soc/mtcmos.h>
#include <stdio.h>
#include <symbols.h>

1
src/soc/mediatek/common/dsi_common.c
View file

@ -5,6 +5,7 @@
#include <device/mmio.h>
#include <delay.h>
#include <edid.h>
#include <soc/display_dsi.h>
#include <soc/dsi.h>
#include <string.h>
#include <timer.h>

55
src/soc/mediatek/common/include/soc/display_dsi.h Normal file
View file

@ -0,0 +1,55 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef SOC_MEDIATEK_DISPLAY_DSI_H
#define SOC_MEDIATEK_DISPLAY_DSI_H
#include <edid.h>
#include <types.h>
enum mipi_dsi_pixel_format {
MIPI_DSI_FMT_RGB888,
MIPI_DSI_FMT_RGB666,
MIPI_DSI_FMT_RGB666_PACKED,
MIPI_DSI_FMT_RGB565
};
/* video mode */
enum {
MIPI_DSI_MODE_VIDEO = BIT(0),
/* video burst mode */
MIPI_DSI_MODE_VIDEO_BURST = BIT(1),
/* video pulse mode */
MIPI_DSI_MODE_VIDEO_SYNC_PULSE = BIT(2),
/* enable auto vertical count mode */
MIPI_DSI_MODE_VIDEO_AUTO_VERT = BIT(3),
/* enable hsync-end packets in vsync-pulse and v-porch area */
MIPI_DSI_MODE_VIDEO_HSE = BIT(4),
/* disable hfront-porch area */
MIPI_DSI_MODE_VIDEO_HFP = BIT(5),
/* disable hback-porch area */
MIPI_DSI_MODE_VIDEO_HBP = BIT(6),
/* disable hsync-active area */
MIPI_DSI_MODE_VIDEO_HSA = BIT(7),
/* flush display FIFO on vsync pulse */
MIPI_DSI_MODE_VSYNC_FLUSH = BIT(8),
/* disable EoT packets in HS mode */
MIPI_DSI_MODE_EOT_PACKET = BIT(9),
/* device supports non-continuous clock behavior (DSI spec 5.6.1) */
MIPI_DSI_CLOCK_NON_CONTINUOUS = BIT(10),
/* transmit data in low power */
MIPI_DSI_MODE_LPM = BIT(11),
/* dsi per line's data end same time on all lanes */
MIPI_DSI_MODE_LINE_END = BIT(12),
/* mipi is in CPHY mode */
MIPI_DSI_MODE_CPHY = BIT(13),
/* mipi is DSI Dual Channel mode */
MIPI_DSI_DUAL_CHANNEL = BIT(14),
/* mipi is DSC compression mode */
MIPI_DSI_DSC_MODE = BIT(15),
};
/* Public API for common display code (display.c). */
int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,
const u8 *init_commands);
#endif /* SOC_MEDIATEK_DISPLAY_DSI_H */

49
src/soc/mediatek/common/include/soc/dsi_common.h
View file

@ -8,48 +8,7 @@
#include <mipi/dsi.h>
#include <types.h>
#include <soc/addressmap.h>
enum mipi_dsi_pixel_format {
MIPI_DSI_FMT_RGB888,
MIPI_DSI_FMT_RGB666,
MIPI_DSI_FMT_RGB666_PACKED,
MIPI_DSI_FMT_RGB565
};
/* video mode */
enum {
MIPI_DSI_MODE_VIDEO = BIT(0),
/* video burst mode */
MIPI_DSI_MODE_VIDEO_BURST = BIT(1),
/* video pulse mode */
MIPI_DSI_MODE_VIDEO_SYNC_PULSE = BIT(2),
/* enable auto vertical count mode */
MIPI_DSI_MODE_VIDEO_AUTO_VERT = BIT(3),
/* enable hsync-end packets in vsync-pulse and v-porch area */
MIPI_DSI_MODE_VIDEO_HSE = BIT(4),
/* disable hfront-porch area */
MIPI_DSI_MODE_VIDEO_HFP = BIT(5),
/* disable hback-porch area */
MIPI_DSI_MODE_VIDEO_HBP = BIT(6),
/* disable hsync-active area */
MIPI_DSI_MODE_VIDEO_HSA = BIT(7),
/* flush display FIFO on vsync pulse */
MIPI_DSI_MODE_VSYNC_FLUSH = BIT(8),
/* disable EoT packets in HS mode */
MIPI_DSI_MODE_EOT_PACKET = BIT(9),
/* device supports non-continuous clock behavior (DSI spec 5.6.1) */
MIPI_DSI_CLOCK_NON_CONTINUOUS = BIT(10),
/* transmit data in low power */
MIPI_DSI_MODE_LPM = BIT(11),
/* dsi per line's data end same time on all lanes */
MIPI_DSI_MODE_LINE_END = BIT(12),
/* mipi is in CPHY mode */
MIPI_DSI_MODE_CPHY = BIT(13),
/* mipi is DSI Dual Channel mode */
MIPI_DSI_DUAL_CHANNEL = BIT(14),
/* mipi is DSC compression mode */
MIPI_DSI_DSC_MODE = BIT(15),
};
#include <soc/display_dsi.h>
static struct dsi_regs *const dsi0 = (void *)DSI0_BASE;
@ -209,8 +168,8 @@ void mtk_dsi_reset(void);
void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing);
/*
* Public API provided in common/dsi_common.c, common/dsi_v1.c, and
* common/mtk_mipi_{c/d}phy.c
* DSI-internal APIs provided in common/dsi_common.c, common/dsi_v1.c,
* and common/mtk_mipi_{c/d}phy.c
*/
void mtk_dsi_cphy_enable(void);
void mtk_dsi_cphy_enable_cmdq_6byte(void);
@ -224,7 +183,5 @@ void mtk_dsi_cphy_disable_ck_mode(void);
void mtk_dsi_dphy_disable_ck_mode(void);
void mtk_dsi_dphy_timing_calculation(u32 data_rate_mhz, struct mtk_phy_timing *timing);
void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes, bool is_cphy);
int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,
const u8 *init_commands);
#endif /* SOC_MEDIATEK_DSI_COMMON_H */

8
src/soc/mediatek/mt8195/include/soc/dsi.h
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@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef SOC_MEDIATEK_MT8195_DSI_H
#define SOC_MEDIATEK_MT8195_DSI_H
#include <soc/dsi_common.h>
#endif