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soc/amd/common/acpi/lpc.asl: Report fixed base addresses

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On systems with AMD ROM armor enabled the SPI base address register
in LPC bridge PCI device space is not accessible (returns all FFs).
In such case the AML code will not be able to retrieve the SPI BAR
and report it properly. Use fixed bases instead to avoid running
into this problem in the future.

Change-Id: Ia01508e5ddf2da053f9bf4116c5e05b89500f772
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89488
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michał Żygowski 2025-10-06 12:09:46 +02:00
commit 3053cd2dad
1 changed files with 4 additions and 8 deletions
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12
src/soc/amd/common/acpi/lpc.asl
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@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/iomap.h>
#if MAINBOARD_HAS_SPEAKER
#define IO61_HID "PNP0800" /* AT style speaker */
#else
@ -14,10 +16,6 @@ Device(LPCB) {
* DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
} */ /* End Method(_SB.SBRDG._INI) */
OperationRegion(CFG,PCI_Config,0x0,0x100) // Map PCI Configuration Space
Field(CFG,DWordAcc,NoLock,Preserve){
Offset(0xA0),
BAR,32} // SPI Controller Base Address Register (Index 0xA0)
Device(LDRC) // LPC device: Resource consumption
{
@ -42,10 +40,8 @@ Device(LPCB) {
{
CreateDwordField(^CRS,^BAR0._BAS,SPIB) // Field to hold SPI base address
CreateDwordField(^CRS,^BAR1._BAS,ESPB) // Field to hold eSPI base address
Local0 = BAR & 0xffffff00
SPIB = Local0 // SPI base address mapped
Local1 = Local0 + 0x10000
ESPB = Local1 // eSPI base address mapped
SPIB = SPI_BASE_ADDRESS // SPI base address mapped
ESPB = SPIB + 0x10000 // eSPI base address mapped
Return(CRS)
}
}