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soc/mediatek/common: Rename mipi_tx to mipi_tx0

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In preparation for the upcoming DSI dual channel support, where mipi_tx1
will be added, rename mipi_tx to mipi_tx0.

BUG=b:424782827
TEST=emerge-skywalker coreboot
BRANCH=none

Change-Id: Idcbcc9e71bd3657f543d97b70bf875af907da328
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90448
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Yu-Ping Wu 2025-12-10 23:48:11 +08:00 • committed by Yu-Ping Wu
commit 7ef424c75e
4 changed files with 23 additions and 23 deletions
Download patch file Download diff file Expand all files Collapse all files

26
src/soc/mediatek/common/dsi_v1.c
View file

@ -30,34 +30,34 @@ void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes, bool is_cphy)
if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
mtk_dsi_cphy_lane_sel_setting();
clrbits32(&mipi_tx->pll_con4, BIT(11) | BIT(10));
setbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_PWR_ON);
clrbits32(&mipi_tx0->pll_con4, BIT(11) | BIT(10));
setbits32(&mipi_tx0->pll_pwr, AD_DSI_PLL_SDM_PWR_ON);
udelay(30);
clrbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_ISO_EN);
clrbits32(&mipi_tx0->pll_pwr, AD_DSI_PLL_SDM_ISO_EN);
pcw = (u64)data_rate * (1 << txdiv0);
pcw <<= 24;
pcw /= CLK26M_HZ;
write32(&mipi_tx->pll_con0, pcw);
clrsetbits32(&mipi_tx->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8);
write32(&mipi_tx0->pll_con0, pcw);
clrsetbits32(&mipi_tx0->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8);
udelay(30);
setbits32(&mipi_tx->pll_con1, RG_DSI_PLL_EN);
setbits32(&mipi_tx0->pll_con1, RG_DSI_PLL_EN);
/* BG_LPF_EN / BG_CORE_EN */
write32(&mipi_tx->lane_con, 0x3FFF0180);
write32(&mipi_tx0->lane_con, 0x3FFF0180);
udelay(40);
write32(&mipi_tx->lane_con, 0x3FFF00C0);
write32(&mipi_tx0->lane_con, 0x3FFF00C0);
if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
mtk_dsi_cphy_enable();
/* Switch OFF each Lane */
clrbits32(&mipi_tx->d0_sw_ctl_en, DSI_SW_CTL_EN);
clrbits32(&mipi_tx->d1_sw_ctl_en, DSI_SW_CTL_EN);
clrbits32(&mipi_tx->d2_sw_ctl_en, DSI_SW_CTL_EN);
clrbits32(&mipi_tx->d3_sw_ctl_en, DSI_SW_CTL_EN);
clrbits32(&mipi_tx->ck_sw_ctl_en, DSI_SW_CTL_EN);
clrbits32(&mipi_tx0->d0_sw_ctl_en, DSI_SW_CTL_EN);
clrbits32(&mipi_tx0->d1_sw_ctl_en, DSI_SW_CTL_EN);
clrbits32(&mipi_tx0->d2_sw_ctl_en, DSI_SW_CTL_EN);
clrbits32(&mipi_tx0->d3_sw_ctl_en, DSI_SW_CTL_EN);
clrbits32(&mipi_tx0->ck_sw_ctl_en, DSI_SW_CTL_EN);
if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
mtk_dsi_cphy_disable_ck_mode();

2
src/soc/mediatek/common/include/soc/mipi_tx_reg_v1.h
View file

@ -39,7 +39,7 @@ check_member(mipi_tx_regs, phy_sel[0], 0x40);
check_member(mipi_tx_regs, phy_sel[3], 0x4C);
check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544);
static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX0_BASE;
static struct mipi_tx_regs *const mipi_tx0 = (void *)MIPITX0_BASE;
/* Register values */
#define DSI_CK_CKMODE_EN BIT(0)

16
src/soc/mediatek/common/mtk_mipi_cphy.c
View file

@ -19,22 +19,22 @@
void mtk_dsi_cphy_lane_sel_setting(void)
{
write32(&mipi_tx->phy_sel[0], MIPITX_CPHY_LANE_SEL0_SETTING);
write32(&mipi_tx->phy_sel[1], MIPITX_CPHY_LANE_SEL1_SETTING);
write32(&mipi_tx->phy_sel[2], MIPITX_CPHY_LANE_SEL2_SETTING);
write32(&mipi_tx->phy_sel[3], MIPITX_CPHY_LANE_SEL3_SETTING);
write32(&mipi_tx0->phy_sel[0], MIPITX_CPHY_LANE_SEL0_SETTING);
write32(&mipi_tx0->phy_sel[1], MIPITX_CPHY_LANE_SEL1_SETTING);
write32(&mipi_tx0->phy_sel[2], MIPITX_CPHY_LANE_SEL2_SETTING);
write32(&mipi_tx0->phy_sel[3], MIPITX_CPHY_LANE_SEL3_SETTING);
}
void mtk_dsi_cphy_enable(void)
{
setbits32(&mipi_tx->lane_con, DSI_CPHY_EN);
setbits32(&mipi_tx0->lane_con, DSI_CPHY_EN);
}
void mtk_dsi_cphy_disable_ck_mode(void)
{
clrsetbits32(&mipi_tx->voltage_sel, DSI_HSTX_LDO_REF_SEL, 0xF << 6);
clrbits32(&mipi_tx->ck_ckmode_en, DSI_CK_CKMODE_EN);
setbits32(&mipi_tx->lane_con, DE_EMPHASIS_EN);
clrsetbits32(&mipi_tx0->voltage_sel, DSI_HSTX_LDO_REF_SEL, 0xF << 6);
clrbits32(&mipi_tx0->ck_ckmode_en, DSI_CK_CKMODE_EN);
setbits32(&mipi_tx0->lane_con, DE_EMPHASIS_EN);
}
void mtk_dsi_cphy_enable_cmdq_6byte(void)

2
src/soc/mediatek/common/mtk_mipi_dphy.c
View file

@ -5,5 +5,5 @@
void mtk_dsi_dphy_disable_ck_mode(void)
{
setbits32(&mipi_tx->ck_ckmode_en, DSI_CK_CKMODE_EN);
setbits32(&mipi_tx0->ck_ckmode_en, DSI_CK_CKMODE_EN);
}