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soc/amd/glinda: Add XGBE devices

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Some specific Glinda SoCs support dual 10G PCI ethernet devices.
Add defines and chipset entries for XGBE0 and XGBE1.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7e3bb1819165a7c2f4284b76450f831bb99b1ad3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90416
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Rudolph 2025-07-25 10:14:08 +02:00 • committed by Felix Held
commit 9e5c7eb3f8
2 changed files with 10 additions and 0 deletions
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2
src/soc/amd/glinda/chipset.cb
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@ -60,6 +60,8 @@ chip soc/amd/glinda
ops amd_internal_pcie_gpp_ops
device pci 0.0 on end # dummy, do not disable
device pci 0.1 alias npu off end # Neural Processing Unit (NPU)
device pci 0.2 alias xgbe_0 off end # 10 GbE Controller Port 0 (XGBE0)
device pci 0.3 alias xgbe_1 off end # 10 GbE Controller Port 1 (XGBE1)
end
device pci 08.3 alias gpp_bridge_c on # Internal GPP Bridge 2 to Bus C

8
src/soc/amd/glinda/include/soc/pci_devs.h
View file

@ -81,6 +81,14 @@
#define PCIE_GPP_B_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_B_FUNC)
#define SOC_PCIE_GPP_B_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_B_FUNC)
#define XGBE0_DEV 0x0
#define XGBE0_FUNC 2
#define XGBE0_DEVFN PCI_DEVFN(XGBE0_DEV, XGBE0_FUNC)
#define XGBE1_DEV 0x0
#define XGBE1_FUNC 3
#define XGBE1_DEVFN PCI_DEVFN(XGBE1_DEV, XGBE1_FUNC)
#define PCIE_ABC_C_FUNC 3
#define PCIE_ABC_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC)
#define SOC_PCIE_GPP_C_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC)