soc/amd/glinda/Kconfig: Add Faegan SoC as Glinda variant
Glinda and Faegan are closely related and there's only very minimal difference from the coreboot viewpoint, so Feagan is added as Glianda variant and not as a new SoC folder. Faegan has a different CPUID, so it's added to the CPU table, and some GPIO muxes have a few more valid settings to route the MDIO pins related to the 2 XGBE controllers to GPIO pins. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I57699089a4a3ac7ddb037f254d42cb043b816c55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/90417 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Rudolph
Felix Held
parent
9e5c7eb3f8
commit
244e8edf18
5 changed files with 70 additions and 7 deletions
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@ -3,7 +3,7 @@
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# TODO: Evaluate what can be moved to a common directory
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# TODO: Update for Glinda
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config SOC_AMD_GLINDA
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config SOC_AMD_GLINDA_BASE
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bool
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select ACPI_SOC_NVS
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select ARCH_X86
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@ -96,7 +96,19 @@ config SOC_AMD_GLINDA
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help
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AMD Glinda support
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if SOC_AMD_GLINDA
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config SOC_AMD_GLINDA
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bool
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select SOC_AMD_GLINDA_BASE
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help
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AMD Glinda support
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config SOC_AMD_FAEGAN
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bool
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select SOC_AMD_GLINDA_BASE
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help
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AMD Faegan support
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if SOC_AMD_GLINDA_BASE
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config CHIPSET_DEVICETREE
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string
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@ -451,4 +463,4 @@ config RWB_REGION_ONLY
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endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK
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endif # SOC_AMD_GLINDA
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endif # SOC_AMD_GLINDA_BASE
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@ -3,7 +3,7 @@
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# TODO: Move as much as possible to common
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# TODO: Update for Glinda
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ifeq ($(CONFIG_SOC_AMD_GLINDA),y)
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ifeq ($(CONFIG_SOC_AMD_GLINDA_BASE),y)
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subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage
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@ -315,4 +315,4 @@ build_complete:: $(obj)/amdfw_a.rom $(obj)/amdfw_b.rom
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endif # CONFIG_SEPARATE_SIGNED_PSPFW
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endif
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endif # ($(CONFIG_SOC_AMD_GLINDA),y)
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endif # ($(CONFIG_SOC_AMD_GLINDA_BASE),y)
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@ -17,6 +17,7 @@ static struct device_operations cpu_dev_ops = {
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static struct cpu_device_id cpu_table[] = {
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{ X86_VENDOR_AMD, GLINDA_A0_CPUID, CPUID_ALL_STEPPINGS_MASK },
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{ X86_VENDOR_AMD, GLINDA_B0_CPUID, CPUID_ALL_STEPPINGS_MASK },
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{ X86_VENDOR_AMD, FAEGAN_A0_CPUID, CPUID_ALL_STEPPINGS_MASK },
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CPU_TABLE_END
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};
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@ -3,6 +3,8 @@
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#ifndef AMD_GLINDA_CPU_H
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#define AMD_GLINDA_CPU_H
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#define GLINDA_A0_CPUID CPUID_FROM_FMS(0x1a, 0x20, 0)
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#define GLINDA_B0_CPUID CPUID_FROM_FMS(0x1a, 0x24, 0)
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#define GLINDA_A0_CPUID CPUID_FROM_FMS(0x1a, 0x20, 0x0)
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#define GLINDA_B0_CPUID CPUID_FROM_FMS(0x1a, 0x24, 0x0)
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#define FAEGAN_A0_CPUID CPUID_FROM_FMS(0x1a, 0x68, 0x0)
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#endif /* AMD_GLINDA_CPU_H */
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@ -115,18 +115,27 @@
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#define GPIO_4_IOMUX_GPIOxx 0
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#define GPIO_5_IOMUX_GPIOxx 0
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#define GPIO_6_IOMUX_GPIOxx 0
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#if CONFIG(SOC_AMD_FAEGAN)
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#define GPIO_6_IOMUX_MDIO0_SCL 2
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#endif
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#define GPIO_7_IOMUX_GPIOxx 0
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#define GPIO_7_IOMUX_ZST_STUTTER_RAIL 1
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#define GPIO_8_IOMUX_GPIOxx 0
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#define GPIO_8_IOMUX_TMU_CLK_OUT0 1
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#define GPIO_8_IOMUX_TMU_CLK_OUT1 2
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#define GPIO_9_IOMUX_GPIOxx 0
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#if CONFIG(SOC_AMD_FAEGAN)
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#define GPIO_9_IOMUX_MDIO2_SCL 2
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#endif
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#define GPIO_10_IOMUX_GPIOxx 0
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#define GPIO_10_IOMUX_S0A3_GPIO 1
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/* GPIO 10 IOMUX == 2 is also GPIOxx */
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#define GPIO_10_IOMUX_DF_VRCONTEXT_0 3
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#define GPIO_11_IOMUX_GPIOxx 0
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#define GPIO_11_IOMUX_BLINK 1
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#if CONFIG(SOC_AMD_FAEGAN)
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#define GPIO_11_IOMUX_MDIO3_SDA 2
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#endif
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#define GPIO_12_IOMUX_LLB_L 0
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#define GPIO_12_IOMUX_GPIOxx 1
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#define GPIO_16_IOMUX_USB_OC0_L 0
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@ -152,6 +161,9 @@
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#define GPIO_22_IOMUX_SD0_CMD 3
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#define GPIO_23_IOMUX_AC_PRES 0
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#define GPIO_23_IOMUX_GPIOxx 1
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#if CONFIG(SOC_AMD_FAEGAN)
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#define GPIO_23_IOMUX_MDIO2_SDA 2
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#endif
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#define GPIO_24_IOMUX_USB_OC3_L 0
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#define GPIO_24_IOMUX_GPIOxx 1
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#define GPIO_26_IOMUX_PCIE_RST0_L 0
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@ -169,11 +181,23 @@
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#define GPIO_31_IOMUX_SPI2_CS3_L 3
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#define GPIO_32_IOMUX_GPIOxx 0
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#define GPIO_32_IOMUX_LPC_RST_L 1
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#if CONFIG(SOC_AMD_FAEGAN)
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#define GPIO_32_IOMUX_MDIO3_SCL 2
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#endif
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#define GPIO_38_IOMUX_CLK_REQ5_L 0
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#define GPIO_38_IOMUX_GPIOxx 1
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#if CONFIG(SOC_AMD_FAEGAN)
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#define GPIO_38_IOMUX_MDIO1_SDA 2
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#endif
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#define GPIO_39_IOMUX_CLK_REQ6_L 0
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#define GPIO_39_IOMUX_GPIOxx 1
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#if CONFIG(SOC_AMD_FAEGAN)
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#define GPIO_39_IOMUX_MDIO1_SCL 2
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#endif
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#define GPIO_40_IOMUX_GPIOxx 0
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#if CONFIG(SOC_AMD_FAEGAN)
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#define GPIO_40_IOMUX_MDIO0_SDA 2
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#endif
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#define GPIO_42_IOMUX_GPIOxx 0
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#define GPIO_42_IOMUX_DF_VRCONTEXT_1 1
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#define GPIO_67_IOMUX_SPI_ROM_REQ 0
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@ -257,13 +281,22 @@
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#define GPIO_135_IOMUX_UART3_TXD 2
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#define GPIO_136_IOMUX_GPIOxx 0
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#define GPIO_136_IOMUX_UART2_RXD 1
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#if CONFIG(SOC_AMD_FAEGAN)
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#define GPIO_136_IOMUX_XGBE_LED0 2
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#endif
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#define GPIO_137_IOMUX_GPIOxx 0
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#define GPIO_137_IOMUX_UART2_RTS_L 1
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#define GPIO_137_IOMUX_UART3_RXD 2
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#define GPIO_138_IOMUX_GPIOxx 0
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#define GPIO_138_IOMUX_UART2_TXD 1
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#if CONFIG(SOC_AMD_FAEGAN)
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#define GPIO_138_IOMUX_XGBE_LED1 2
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#endif
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#define GPIO_139_IOMUX_GPIOxx 0
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#define GPIO_139_IOMUX_UART2_INTR 1
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#if CONFIG(SOC_AMD_FAEGAN)
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#define GPIO_139_IOMUX_XGBE_LED2 2
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#endif
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#define GPIO_140_IOMUX_GPIOxx 0
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#define GPIO_140_IOMUX_UART0_CTS_L 1
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#define GPIO_140_IOMUX_UART1_TXD 2
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@ -291,13 +324,28 @@
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#define GPIO_148_IOMUX_GPIOxx 2
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#define GPIO_153_IOMUX_GPIOxx 0
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#define GPIO_153_IOMUX_UART4_CTS_L 1
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#if CONFIG(SOC_AMD_FAEGAN)
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#define GPIO_153_IOMUX_XGBE_LED3 2
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#endif
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#define GPIO_154_IOMUX_GPIOxx 0
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#define GPIO_154_IOMUX_UART4_RTS_L 1
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#if CONFIG(SOC_AMD_FAEGAN)
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#define GPIO_154_IOMUX_XGBE_LED4 2
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#endif
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#define GPIO_155_IOMUX_GPIOxx 0
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#define GPIO_155_IOMUX_UART4_RXD 1
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#if CONFIG(SOC_AMD_FAEGAN)
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#define GPIO_155_IOMUX_XGBE_LED5 2
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#endif
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#define GPIO_156_IOMUX_GPIOxx 0
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#define GPIO_156_IOMUX_UART4_TXD 1
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#if CONFIG(SOC_AMD_FAEGAN)
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#define GPIO_156_IOMUX_XGBE_LED6 2
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#endif
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#define GPIO_157_IOMUX_GPIOxx 0
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#define GPIO_157_IOMUX_UART4_INTR 1
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#if CONFIG(SOC_AMD_FAEGAN)
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#define GPIO_157_IOMUX_XGBE_LED7 2
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#endif
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#endif /* AMD_GLINDA_GPIO_H */
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