Enabling MMCONF is simple and should be done first to allow bootblock
code to access the PCI config space. Required to cache ROM3 in
early_cache_setup() that is now called directly after enabling MMCONF.
Change-Id: I5d5f533258985211afafd9bf748f8e26f6128bd4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86619
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On x86_64 use the ROM3 window to access the SPI flash. Use the
same mechanism as on Intel, where the lower 16Mbyte are mapped
using ROM2 window and the upper pages are mapped using the ROM3
window. By default the ROM3 window resides in high MMIO and thus
needs 1024GiB of the address space to be identity mapped in the
page tables.
This allows legacy 32-bit code to work on mappings in the lower
16MiB of the flash chip.
Introduces new messages in coreboot log:
[INFO ] ROM2 Decode Window: SPI flash base=0x0, Host base=0xff000000, Size=0x1000000
[INFO ] ROM3 Decode Window: SPI flash base=0x1000000, Host base=0xfd01000000, Size=0x3000000
TEST: Disabled ROM2 mapping and booted from ROM3 mapping in x86_64
on amd/birman+.
Change-Id: I8976273cfb31765d7f893b3fc137f117c63b6553
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
The E7240 actually has a 8MiB + 4MiB flash configuration, not 8MiB.
Change-Id: I14f0c8f6f0c0dfebf41294812b1f4e131eaa18d0
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit overrides the `logo_valignment` setting in the
`common_soc_config` for the Ocelot board variant, similar to
https://review.coreboot.org/c/coreboot/+/87453.
The vertical alignment for the firmware splash screen logo is now set to
`FW_SPLASH_VALIGNMENT_MIDDLE`, which places the top edge of the logo at
the vertical midpoint of the screen.
Change-Id: I29f08d31d325304f7532ed37f9cf3d5ef0bb88ff
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit removes the `device ref npk on end` from the
`overridetree.cb` files for ocelot, similar to -
commit 85c65b0c20 (mb/google/fatcat: Remove NPK device from fatcat and francka variants)
This effectively disables the NPK device for these configurations
(because `npk` is default set to disable).
Change-Id: Iee1509f44f6543c23f9633ccd8d35d4a7e37b89e
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87753
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When the number of eFuse reads exceeds a certain limit (with a maximum
of 20 million), a bit flip from 1 to 0 may happen. When that happens,
the bit flip will be automatically corrected by the eFuse hardware via
ECC (Error Correction Code), and the EFUSE_ECC_ERR register bit will be
set for the software to decide how to handle that.
Therefore, this patch adds a check for the EFUSE_ECC_ERR register bit.
If it's set due to a bit flip instead of a real error, we simply clear
it to avoid triggering a WDT reset.
BUG=b:379008996
BRANCH=none
TEST=build passed and check the WDT status debug log. This log is added
in local for test only.
[INFO ] mtk_wdt_clear_efuse_ecc: wdt_sta = 0x0
Signed-off-by: Zexin Wang <ot_zexin.wang@mediatek.corp-partner.google.com>
Change-Id: Idd2763688c7ab6992a7c185e9e52b60bda88c94c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87744
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
crrev/c/5828162 introduced vccin_aux_imon_iccmax parameter for each variant to override the VccInAuxImonIccImax FSP parameter to follow its VCCANA power rail design.
Since meliks adopts external VR design for VCCANA power rail, set it to 25A to follow the guidance in RDC#646929 Power Map.
BUG=b:409205469
TEST=Built and boot
Verified maximum 5% of 3D mark score improvement on N250 SKU
Change-Id: I58786493098c787d402c85ce7167319285af7488
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87704
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, it was found that the GPP_D2 and GPP_D18 pins affect power
consumption during S0ix. After discussion with the hardware team,
since the motherboard is shared across different platforms and these
two pins are unused on the Chrome platform, they will be set to NC.
Measurements have shown that this change effectively improves power
consumption.
Due to some pins changes for next phase, the modifications are listed
below for reference.
Follow the GPIO table updated on 05/19.
GPP_D2 : GPO -> NC
GPP_D14:
Current phase: GPO -> NC
Next phase : FUNC1 (UART0_ISH)
GPP_D18:
Current phase: FUNC2 (UART1_ISH)
Next phase : GPO -> NC
BUG=b:411554553
TEST=improve 375mW-->143mW
Change-Id: I3c788ed4e2ff3e5d49008c03a895d13549d5c79b
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87709
Reviewed-by: Ben Kao <ben.kao@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit removes an unnecessary space in the Kconfig name
for BOARD_GOOGLE_FELINO.
Change-Id: I49044a49fcef914b2e11d3c2eeefe6b6b082d8c1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87749
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move `post_cpus_init` to execute at the entry of the `BS_DEV_ENABLE`
boot state. This function is responsible for synchronizing
and finalizing MTRR (Memory Type Range Registers) settings across all threads.
This change ensures that MTRR configuration occurs at the correct
point in the boot sequence:
- After main DRAM resources are determined and finalized (typically
by the `BS_DEV_RESERVE_RESOURCES` state). MTRRs define
attributes for these physical memory ranges.
Previously, `post_cpus_init` was hooked at `BS_WRITE_TABLES` (on exit)
or `BS_OS_RESUME` (on entry). Relocating to `BS_DEV_ENABLE` (on entry)
provides a more robust and correctly sequenced execution point for this
essential multi-processor (MP) MTRR setup.
BUG=b:413638298
TEST=Successfully built and booted google/fatcat. Verified that
MTRR programming, which depends on DRAM resource determination
(finalized by BS_DEV_RESERVE_RESOURCES), now correctly
executes at BS_DEV_ENABLE, prior to full device initialization.
Change-Id: I1d2b3f11e4ac268c5b35bf9a8062a77a48a0601a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Update header files for FSP for Panther Lake platform to version
3144_01, with the previous version being 3071_00.
Changes include:
- Update UPD Offset in FspmUpd.h and FspsUpd.h.
- Update MemInfoHob.h:
- Update MEMORY_INFO_DATA_HOB, child structures and their data for
SMBIOS type 16/17 design change.
- Add new variable PprFailingChannelBitMask to
MEMORY_INFO_DATA_HOB.
- Update soc/intel/pantherlake/romstage/romstage.c: Refactor coreboot
to match MEMORY_INFO_DATA_HOB data structure.
BUG=b:414734316
TEST=Able to build google/fatcat. Verify that the updates to
MEMORY_INFO_DATA_HOB and its child structures for SMBIOS type 16/17
design changes are correctly integrated from FSP 3144_01 onwards.
Change-Id: I054e419ef23ada67347750e7a68014c2bb112199
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87000
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: <srinivas.kulkarni@intel.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add initialization of DPM driver for DRAM low power mode.
BUG=b:379008996
BRANCH=none
TEST=Boot up pass and see log
3200 LPDDR5 chan0(x16) rank0: memory test pass
3200 LPDDR5 chan0(x16) rank1: memory test pass
3200 LPDDR5 chan1(x16) rank0: memory test pass
3200 LPDDR5 chan1(x16) rank1: memory test pass
Signed-off-by: Mike Lin <mike.lin@mediatek.corp-partner.google.com>
Change-Id: I3b72b892d56623e7f3ec2dccfad073a908b51119
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87663
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
MT8189 equips DPM hardware which is similar to MT8196.
Therefore, we use the same DPM v2 loader to run the blob.
BUG=b:379008996
BRANCH=none
TEST=Make & Boot up pass and see log
mtk_init_mcu: Loaded (and reset) dpm.dm in 19 msecs (1004 bytes)
mtk_init_mcu: Loaded (and reset) dpm.pm in 19 msecs (36588 bytes)
mtk_init_mcu: Loaded (and reset) dpm.dm in 7 msecs (1004 bytes)
mtk_init_mcu: Loaded (and reset) dpm.pm in 19 msecs (36588 bytes)
Signed-off-by: Mike.Lin <mike.lin@mediatek.corp-partner.google.com>
Change-Id: I616cc0880d2db3f94b2a960b11d04974af1e94ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
MT8196 DPM uses broadcast mode for loading DPM bin files. This means
that both dpm.dm and dpm.pm files only need to be loaded once, and
all channels will apply them.
In contrast, MT8189 DPM uses non-broadcast mode, which requires
loading the dpm.dm and dpm.pm files for each channel individually.
The original dpm_v2.c only supports broadcast mode. In this commit,
add support for non-broadcast mode to increase code reusability.
BUG=b:379008996
BRANCH=none
TEST=build passed.
Signed-off-by: Mike Lin <mike.lin@mediatek.corp-partner.google.com>
Change-Id: I599f06c5669f5fd8623966a1c03767ea02b6bd15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87736
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The file was mistakenly left out in the version that got merged, so
internal speakers wouldn't work.
TEST=Boot to Windows 11 and verify internal speakers work
Change-Id: I5529030bb91a41236772ac410096dc6bff00dd32
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87306
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move EC software sync to the SoC code when `VBOOT_EC_SYNC_ESOL` config
is selected. This allows the early Sign-Of-Life (eSOL) to be
displayed during EC firmware update.
`VBOOT_EC_SYNC_SOL` is not coupled with `VBOOT_EARLY_EC_SYNC`,
therefore it can be enabled only for variants whose EC firmware
takes a long time (15-20s) to update.
This change also implements `vboot_show_ec_sync_esol()` function
that displays the eSOL during the update for Alder Lake devices.
AP log during EC firmware update with `VBOOT_EC_SYNC_ESOL` enabled:
```
[INFO ] VB2:check_ec_hash() Heff != Hexp. Schedule update
[0.216229] DP PHY mode status not complete
[0.217189] DP PHY mode status not complete
[INFO ] Informing user on-display of EC software sync.
[DEBUG] FMAP: area COREBOOT found @ c0a000 (4153344 bytes)
[WARN ] CBFS: 'preram_locales' not found.
[INFO ] ux_locales_get_text: preram_locales not found.
[INFO ] VB2:sync_ec() select_rw=RW(active)
[INFO ] VB2:update_ec() Updating RW(active)...
[INFO ] CBFS: Found 'ecrw' @0x1a9f80 size 0x40000 in mcache @0xfef97a9c
[INFO ] VB2:vb2_digest_init() 262144 bytes, hash algo 2, HW acceleration enabled
[INFO ] CBFS: Found 'ecrw.hash' @0x7f8c0 size 0x20 in mcache @0xfef97708
[INFO ] VB2:vb2_digest_init() 32 bytes, hash algo 2, HW acceleration enabled
[INFO ] VB2:check_ec_hash() Hexp RW(active): 62d1d55d26f33bd01a3676656148bedacf44189c81b195ec5488499074fe9bb0
[INFO ] VB2:check_ec_hash() Hmir: 62d1d55d26f33bd01a3676656148bedacf44189c81b195ec5488499074fe9bb0
[WARN ] ec_hash_image: No valid hash (status=0 size=0). Computing...
[INFO ] EC took 482169us to calculate image hash
[INFO ] VB2:check_ec_hash() Heff RW(active): 62d1d55d26f33bd01a3676656148bedacf44189c81b195ec5488499074fe9bb0
[INFO ] VB2:update_ec() Updated RW(active) successfully
[INFO ] VB2:sync_ec() Rebooting to jump to new EC-RW
[INFO ] VB2:vb2api_ec_sync() ec_sync_phase2(ctx) returned 0x1004
[INFO ] EC Reboot requested. Doing cold reboot
```
BUG=b:412210635
TEST=Verify successful EC sync in romstage. Verify eSOL is displayed
during EC update on a nissa (Alder Lake) board by enabling
`VBOOT_EC_SYNC_ESOL` config.
Change-Id: I351d464f2ca64a3e60c52f88c8633e05556c5324
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87670
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change introduces a new Kconfig option `VBOOT_EC_SYNC_ESOL`.
This config can be used to enable the display of early sign-of-life
(eSOL) during EC software sync whenever supported. When this config
is enabled, the EC sync must be performed later from the SoC code
(mainboard_romstage_entry() function) in order to display the eSOL
screen.
This change also adds a hook function vboot_show_ec_sync_esol()
to be run before performing the EC firmware image update during the EC
sync when `VBOOT_EARLY_EC_SYNC` is enabled. This function needs to be
implemented in SoC code when `VBOOT_EC_SYNC_ESOL` is enabled to display
the eSOL and notify the users about the firmware update.
AP log during EC firmware update in romstage:
```
[DEBUG] Google Chrome EC: version:
[DEBUG] ro: pujjo-15217.861.0
[DEBUG] rw: pujjo-15217.861.0
[DEBUG] running image: 1
[DEBUG] FMAP: area FW_MAIN_A found @ 3a2000 (2312128 bytes)
[INFO ] MMAP window: SPI flash base=0x3a0000, Host base=0xff3a0000, Size=0xc60000
[INFO ] CBFS: Found 'ecrw.hash' @0x7f8c0 size 0x20 in mcache @0xfef97708
[INFO ] VB2:vb2_digest_init() 32 bytes, hash algo 2, HW acceleration enabled
[INFO ] VB2:check_ec_hash() Hexp RW(active): 62d1d55d26f33bd01a3676656148bedacf44189c81b195ec5488499074fe9bb0
[INFO ] VB2:check_ec_hash() Hmir: 62d1d55d26f33bd01a3676656148bedacf44189c81b195ec5488499074fe9bb0
[INFO ] EC took 1124us to calculate image hash
[INFO ] VB2:check_ec_hash() Heff RW(active): 8d111297eb53ba2289d256a769409bcbba4cf5b488fea97e40edcc9342a0f77f
[INFO ] VB2:check_ec_hash() Heff != Hexp. Schedule update
[INFO ] VB2:sync_ec() select_rw=RW(active)
[INFO ] VB2:update_ec() Updating RW(active)...
[INFO ] CBFS: Found 'ecrw' @0x1a9f80 size 0x40000 in mcache @0xfef97a9c
[INFO ] VB2:vb2_digest_init() 262144 bytes, hash algo 2, HW acceleration enabled
[INFO ] CBFS: Found 'ecrw.hash' @0x7f8c0 size 0x20 in mcache @0xfef97708
[INFO ] VB2:vb2_digest_init() 32 bytes, hash algo 2, HW acceleration enabled
[INFO ] VB2:check_ec_hash() Hexp RW(active): 62d1d55d26f33bd01a3676656148bedacf44189c81b195ec5488499074fe9bb0
[INFO ] VB2:check_ec_hash() Hmir: 62d1d55d26f33bd01a3676656148bedacf44189c81b195ec5488499074fe9bb0
[WARN ] ec_hash_image: No valid hash (status=0 size=0). Computing...
[INFO ] EC took 482169us to calculate image hash
[INFO ] VB2:check_ec_hash() Heff RW(active): 62d1d55d26f33bd01a3676656148bedacf44189c81b195ec5488499074fe9bb0
[INFO ] VB2:update_ec() Updated RW(active) successfully
[INFO ] VB2:sync_ec() Rebooting to jump to new EC-RW
[INFO ] VB2:vb2api_ec_sync() ec_sync_phase2(ctx) returned 0x1004
[INFO ] EC Reboot requested. Doing cold reboot
```
BUG=b:412210635
TEST=Able to perform successful EC sync when `VBOOT_EARLY_EC_SYNC` is
selected.
Change-Id: Id853c73b54942ab35d4e3f019c1eddf4449c8d3c
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87668
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If the directory specified by CONFIG_CPU_INTEL_UCODE_SPLIT_BINARIES does
not contain any files, no build error will occur, and resulting coreboot
image will not include any microcode.
BUG=None
TEST="src/cpu/intel/microcode/Makefile.mk:16: *** "microcode-params is
empty. Ensure CONFIG_CPU_INTEL_UCODE_SPLIT_BINARIES is set correctly and
contains valid files.". Stop."
Change-Id: I095d9a24cb473b528d85bf8325c06fd3dc055b74
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87636
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
According to the MT6359 datasheet, set the RTC EOSC calibration period
to 8 seconds to ensure that the power source VXO22 in the MT6359 meets
the expected power sequence in AP power-off mode.
BUG=b:397292746
BRANCH=none
TEST=build pass & boot pass
Change-Id: I4043f4e82baeb8e0358e74dd6d088895e4deb0f4
Signed-off-by: Shunxi Zhang <ot_shunxi.zhang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87705
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Don't generate the IVRS ACPI table if the IOMMU PCI device isn't enabled
in the devicetree.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5e7f976011da92c0ca69decdca7aa77de24b6a2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
To promote code reuse and maintainability, move mt8196/sspm_sram.c to
common folder. The macro for the register SSPM_SRAM_CON is replaced by
'mtk_spm->sspm_sram_con' since it is already defined in spm.h.
BUG=b:379008996
BRANCH=none
TEST=build passed.
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I71912a23537a8bb26ed431d06123a875b80b8e4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87661
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The commit 49ae935b37 ("util/abuild: Change [...] to [[...]] for
consistency") [1] accidentally replaced "\>" with ">" in a grep pattern,
causing all boards to be considered not supporting ChromeOS.
The commit f66c7c1037 ("util/abuild: Update echo to printf for
consistency") [2] replaced
@echo $(foreach arch,$(REQUIRED_ARCHES),\
$(if $(filter $(arch),$(SUBARCH_SUPPORTED)),,$(arch)))
with
@printf "%s\n" "$(foreach arch,$(REQUIRED_ARCHES),\
$(if $(filter $(arch),$(SUBARCH_SUPPORTED)),,$(arch)))"
and caused an additional whitespace character to be printed when all
required archs are supported. The result of the `missing_arches` shell
variable would be " ", and hence the `[[ -n "$missing_arches" ]]` check
would be wrong. Fix this by using `-z`.
[1] CB:87367
[2] CB:87368
Change-Id: Ib77566e70ac8b3717f3b29433ce9ae0a1fc69cce
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
This commit updates the flash configuration for the Bluey mainboard
to support the 64MB W25Q512NWEIM SPI flash part.
Key changes:
- Kconfig: The `BOARD_ROMSIZE_KB` selection is changed
from 8192 (8MB) to 65536 (64MB).
These changes ensure the firmware is built correctly for the larger
SPI flash and the flash map accurately reflects the hardware.
BUG=b:404985109
TEST=Able to build google/bluey. Running `ls -l` shows that `coreboot.rom` is 64 MB.
Change-Id: I5acd476989e94fba4022eeb4e96fa50b459b5766
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Removed Kconfig selections for `SPI_FLASH_GIGADEVICE` and
`SPI_FLASH_MACRONIX` from `BOARD_GOOGLE_BLUEY_COMMON`.
This change aligns the configuration with hardware plans, as Bluey
is only intended to support Winbond SPI flash parts. Consequently,
support for GigaDevice and Macronix flash chips is removed.
The `SPI_FLASH_WINBOND` selection remains.
BUG=b:404985109
TEST=Able to build google/bluey.
Change-Id: Ib5f0d40e45f40e694e36cceade75f1f1ac0349c6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87679
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bluey does not have a Chrome EC. This commit adjusts Kconfig settings
and related code to correctly reflect this hardware characteristic,
ensuring Bluey builds and operates appropriately without an EC.
Key changes:
1. Chrome EC Kconfig Optionalized:
- Unconditional selections for `EC_GOOGLE_CHROMEEC`,
`EC_GOOGLE_CHROMEEC_RTC`, `EC_GOOGLE_CHROMEEC_SPI`,
`EC_GOOGLE_CHROMEEC_SWITCHES` (previously selected via `VBOOT`),
and `RTC` have been removed from `BOARD_GOOGLE_BLUEY_COMMON`.
- These are now grouped under a new Kconfig option
`MAINBOARD_HAS_CHROME_EC` (default 'n'). This ensures
EC-related features/APIs are off by default for Bluey.
2. VBoot Adaptation for no-EC:
- `BOARD_GOOGLE_BLUEY` now selects `VBOOT_NO_BOARD_SUPPORT`.
- VBoot relies on board functions (e.g. WP/recovery switches)
often via an EC. `VBOOT_NO_BOARD_SUPPORT` provides stubs
when an EC is absent, allowing vboot to link.
3. Conditional EC Reset Logic:
- `reset.c`: `do_board_reset()` now calls `google_chromeec_reboot()`
only if `CONFIG(EC_GOOGLE_CHROMEEC)` is enabled. This prevents
errors if called when the EC is not configured.
- (Note: Bluey typically selects `MISSING_BOARD_RESET`, so
`reset.c` may not compile. This change makes `reset.c` safer if
used in a no-EC setup without `MISSING_BOARD_RESET`.)
These modifications ensure that Bluey's firmware configuration aligns
with its actual hardware capabilities, specifically its lack of a
Chrome EC.
BUG=b:404985109
TEST=Able to build google/bluey.
Change-Id: Ibee39d76845ce6d9242ade9eacfdb9a8a655c05f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87678
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Bluey board configuration (`BOARD_GOOGLE_BLUEY`) now selects
`MISSING_BOARD_RESET`.
This change is necessary because Bluey does not have a Chrome EC.
Without a Chrome EC, a board-specific `do_board_reset()`
implementation, which often handles system shutdown or reset sequences
by interacting with an EC, is not feasible for Bluey.
As a result of selecting `MISSING_BOARD_RESET`:
- Bluey's `reset.c` is no longer compiled.
- If a board reset is triggered, the system will use the stub
`do_board_reset()` provided when `CONFIG_MISSING_BOARD_RESET`
is enabled.
This aligns Bluey's configuration with its hardware capabilities
regarding system reset.
BUG=b:404985109
TEST=Able to build google/bluey.
Change-Id: I2f770ce9e96544b7e1891a3d8ec84a1313210891
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87677
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces a new Kconfig option `MAINBOARD_HAS_GOOGLE_TPM`
for the Bluey mainboard.
Previously, `I2C_TPM`, `MAINBOARD_HAS_TPM2`, and `TPM_GOOGLE_TI50`
were unconditionally selected within `BOARD_GOOGLE_BLUEY_COMMON`.
These selections are now moved under the new `MAINBOARD_HAS_GOOGLE_TPM`
boolean option, which defaults to disabled.
This change allows for more granular control over enabling Google TPM
(aka GSC) support, making it optional for Bluey configurations.
As Bluey (Qualcomm CRD) lacks a Google TPM (GSC), the new
`MAINBOARD_HAS_GOOGLE_TPM` option defaults to 'n'. This ensures
GSC-related features (including `I2C_TPM`, `MAINBOARD_HAS_TPM2`,
and `TPM_GOOGLE_TI50`) are not selected by default for Bluey,
aligning the Kconfig with the hardware capabilities.
BUG=b:404985109
TEST=Able to build google/bluey. Ensure `VBOOT_MOCK_SECDATA` Kconfig
is default enabled for Bluey.
Change-Id: Idc3d998bfc5a747a3068e87fd2f503190a0c1f3f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The `EC_GOOGLE_CHROMEEC_SPI_BUS` Kconfig and the `GPIO_AP_EC_INT`
setup in `chromeos.c` are now dependent on `EC_GOOGLE_CHROMEEC`.
Similarly, the `MAINBOARD_GPIO_PIN_FOR_GSC_AP_INTERRUPT` Kconfig
and the `GPIO_GSC_AP_INT` setup are now dependent on `TPM_GOOGLE_TI50`.
This ensures that GPIOs are only configured if their respective
features are enabled, preventing potential issues when they are
disabled.
BUG=b:404985109
TEST=Able to build google/bluey.
Change-Id: I44525dd008c42c42aa7e5c4a4f290b09312ed269
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87674
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SMBUS_CLK0/DAT0 need to be pulled high on SOC Side according to schematics revision 20241120.
otherwise board cannot enter s0ix due to SMBUS blocking.
BUG=b:403383143
TEST=emerge-fatcat coreboot and machine can enter the s0ix state.
Change-Id: Iac4ca81601331ac35705a73c13ede8efb89ab370
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Move function declarations to dpm_common.h, which is shared for both
dpm_v1 and dpm_v2. Add a new function dpm_init_mcu() to the header to
reduce duplicate code in dpm_v1.c, dpm_v2.c and dpm_4ch.c.
BUG=none
TEST=emerge-skywalker coreboot
BRANCH=none
Change-Id: I8d6318e9c3c4570cb8f3ff64242fc414770db653
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Configure GPIO XHCI_INIT_DONE as output, so that payloads (for example
depthcharge) can assert it to notify EC to enable USB VBUS.
BUG=b:379008996
BRANCH=none
TEST=build passed
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I054dad3783b7fd3c9b00003de9c3333759b8e44a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87657
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the pujjolo variant of nissa reference board by copying the
template files to a new directory named for the variant.
Due to new_variant.py limitation that repo can no longer be used in
inside, created this CL manually following google suggestion.
BUG=b:395763555
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_PUJJOLO
Change-Id: Ica959c0e22797ab75606af130fa1adff2b158b1d
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87470
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In CB:87370 (util/abuild: Use ${} around variable names),
commit id: a2baaec067, some lines were unintentionally reordered.
This led to abuild not working as intended.
Change-Id: I0aced8dde475f7338e4670c11a9cd1ec4502d743
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87681
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Much like ongoing CFR work, this patch adds support for configuring
certain options (such as iGPU memory allocation, ASPM, S3/s0ix, VT-d) at
runtime, using EDK2 payload.
TEST=Build/boot/toggle coreboot+edk2 on the firewall, test results by
booting Linux.
Change-Id: Id51e704750fd9aa4a8df72804d9205974747d708
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87652
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
When using the CFR option backend, a mainboard may want to set the ME
default state to disabled, so add a Kconfig which can be selected to do
so.
Change-Id: I53d88af5e5cc9b7300b847e4aaf8e4cd2ce5bb75
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87649
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
Change-Id: I572f119c86ea0e2a16d4bb543bc61afab423d092
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
