USB port 0 (P0) is force_suspended during the BootROM stage, and this
state won't be cleared in subsequent stages, causing P0 to become
unusable. Adding the P0 controller in coreboot ensures that the
force_suspended state is cleared, restoring P0 functionality.
BUG=b:417079837
BRANCH=None
TEST=Build passes and insert a USB device into USB port 0 can enumerate
the USB device.
Signed-off-by: Liu Liu <ot_liu.liu@mediatek.corp-partner.google.com>
Change-Id: Ibe8649297d3236a8896d1045cdf23cb4b1313e43
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The GPIO which is used to determine whether the keyboard is connected
or not is dual-edge triggered, not level triggered, so adjust the
method name to reflect that. This ensures that the keyboard status
is updated on both connection and disconnection.
TEST=build/boot starlite_adl, verify tablet mode is correctly detected
when the keyboard is detached under both Windows and Linux.
Change-Id: I6c539fa264a2910589846e58d851acbe7c00900e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
PMC_GPP_F and GPP_F resolve to the same thing, but use the latter for
consistency and clarity. Non-functional change.
Change-Id: I005221cf7289ad2090b4231755d2eb4766bf67fe
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87992
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Was masking the correct value set previously.
Change-Id: Ibe88fe4ad0de68b1188ec6a526497d5c0d75e56f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The option hooks are already set up at the SoC level, so
just add a new CFR form to expose the configuration.
Change-Id: I423e6b617ba60d7e44064ad9f4c3fec7e3e3fe75
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Use SoC common CFR forms where available.
Change-Id: I05106aca4402ec977a4593a4523dd7f30156b96c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
According to the circuit schematic diagram, pujjocento uses GPP_E12
as a write-protected gpio,so it is necessary to add the GPIO_PCH_WP
definition for GPP_E12 in gpio.h.
BUG=b:422656149
BRANCH=none
TEST=wp status update verified by toggling it on and off.
Change-Id: I91081f1b0ce5cb2fb3a29b96c1dcc18774f70f09
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
darp11 is an ArrowLake-H refresh of the previous model.
Change-Id: I1ac692a6591e0c7df89c5ba76a83764694145762
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87675
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Nit-pick tidy up, for things like indentation and using true/false for bools.
Change-Id: Icae88494306b48695e69fd878e11e648327b443d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These boards only ever used one trackpad, so there is no need for this
to be set.
Change-Id: Ibabb663a83eea5f06c683cf2854ceed0487baf51
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This provides entries in the SSDT for all display devices, which
allows the kernel to enumerate them.
Change-Id: Idfa688c3497aa91a9fa5c7923cff04a7ec4892ed
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87947
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is not used, so remove it.
Change-Id: I5d576833c634cc4d2e9eb01627f9bdb61d764b13
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This provides entries in the SSDT for all display devices, which
allows the kernel to enumerate them.
Change-Id: Ic6c5578d6995aacfff548d10083a712a0faca622
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87943
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Put the GPIOs into groups with clear comments.
Change-Id: I7246fee8bdf111bc08c1335a90609e94356fc611
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
GPIOs, like the USB overcurrent ones, are not used so configure them accordingly.
Change-Id: If5138ccd6048f006408d5335439e7a0143c9cc28
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Configure all strap GPIOs as outputs, rather than some being not
connected. This doesn't change anything, but is more explicit.
Set these all to sample on RSMRST.
Change-Id: I693cfecdb73a20b76fa040500eed5d904b857710
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Remove the configuration for the vGPIOs, as it is not needed because
FSP handles it.
Change-Id: I8831379ffd8c9df00736cb62512e023592d0d301
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The Byte Mk III is the same, apart from using the Twin Lane N355 instead
of the N200, which means 99.99% of the code is the same.
Change-Id: Ia31f905bea7a6efdad1ed4e36361059ceea2a1ed
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This version of the VBT works for Alder Lake N and Twin Lake.
Change-Id: Ia2161a04018ec3e222a2751b42fe63637b05e6dd
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87895
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In TWL, Type-C0 corresponds to TCSS port1, and Type-C1 corresponds
to TCSS port0. In order for the DP functions of the two Type-C ports
to operate normally, the corresponding relationship needs to be
configured correctly.
BUG=b:418106736
TEST=DP function of Type-C0/C1 workable
Change-Id: I4aa406e72d1e5f0434866b105f20df6362f3d304
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87899
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: hualin wei <weihualin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This patch removes the power limit override code from google/ocelot until the power limits for WCL are known. It is left as a TODO till then.
Change-Id: I15bd1a1c8397957df96a97b4f9f3de0fd5f5c7f6
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Use the storage type from fw_config to determine which types of storage
need to be set up in the payload.
BUG=b:379008996
BRANCH=none
TEST=input "cbi set 6 0x40000000 4" in ec console, and see the
following log:
fw_config match found: STORAGE=STORAGE_UFS2X
storage_setup: eMMC: no, UFS: yes
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ieada3c56b0f69cc1ea3dab4e64641bfc2ba2a0fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87923
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Skywalker reference design supports multiple storage types, such as UFS
and eMMC. We only need to configure eMMC if the board storage type is
eMMC.
BUG=b:379008996
BRANCH=none
TEST=build pass
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I7c3a2e3f7acf75d57d72cda3c9d2e83b77c72f0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87922
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Add the initialization in romstage.
BUG=b:410763782
BRANCH=none
TEST=Check the CPU frequencies are changing and not fixed values by
using the following commands in kernel:
1) set policy*/scaling_governor as "ondemand"
"echo ondemand > /sys/devices/system/cpu/cpufreq/policy0/scaling_governor"
"echo ondemand > /sys/devices/system/cpu/cpufreq/policy6/scaling_governor"
2) Check the CPU frequencies by repeating the command
"grep . /sys/devices/system/cpu/cpufreq/policy*/scaling_cur_freq"
The result is like
/sys/devices/system/cpu/cpufreq/policy0/scaling_cur_freq:650000
/sys/devices/system/cpu/cpufreq/policy6/scaling_cur_freq:2350000
Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Change-Id: Ie64ebd1b78096c38c4398572cbed3e2e9ac6b8b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87917
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
This are a bit illogical, so tidy them up.
Change-Id: Idd4f616181949780c042142344b3bbbccc4f15f6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87894
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Add serial_io_i2c_mode to fix can not boot up to OS issue.
2. Change level from low to high to fix parade touchscreen issue.
BUG=b:395763555
BRANCH=none
TEST=Build and boot to pujjolo. Verify functions work.
Change-Id: Ic0a02daa39f4d1d0287115ecab12f45201704227
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87909
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The bootblock size for the Google Bluey mainboard has been increased
from 96KB to 120KB.
This change is necessary to accommodate the growing size of the
bootblock image, which now exceeds the previous 96KB limit. This
expansion ensures that the complete bootblock code, including critical
initialization routines and potentially new features, fits within its
allocated flash region.
TEST=Able to build google/quenbi.
Change-Id: I7bf2c8c6c540327f1b4233ee5ba4e0703d1200f9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87903
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Derive the audio amplifier from FW_CONFIG, and set up I2C and I2S for
RT1019.RT1019 and RT9123 use the same GPIOs on the Skywalker reference
design, so the same function is used to improve code reusability. Also
pass the corresponding GPIO to the payload.
BUG=b:417083722
BRANCH=none
TEST=Build pass and test with Depthcharge change:
https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/+/6437675
Check audio cmd in depthcharge with:
firmware-shell: AUDIO CMD=audio 500 100 1
Change-Id: I512cd5c8635d08c6b6c54f04d11bf87c64d1b843
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Derive the audio amplifier from FW_CONFIG, and set up I2C and I2S
for ALC5645. Also pass the corresponding GPIO to the payload.
BUG=b:359705470
BRANCH=none
TEST=build ok and test audio cmd ok
AUDIO CMD=audio 500 100 1
Signed-off-by: Cyril Chao <cyril.chao@mediatek.corp-partner.google.com>
Change-Id: Ib53175f559eecb3d8b5104b12dabfd4793f65d08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Modify USB related settings according to the proto schematic diagram.
BUG=b:409254508
BRANCH=none
TEST=emerge-nissa coreboot chromeos-bootimage,tested USBA and TYPEC function is ok.
Change-Id: I48ec269b612602578b35eeaedffd1a3d311bb97e
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87834
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit populates the `board_id()` and `sku_id()` functions
for the Google Bluey mainboard, replacing the previous placeholder
implementations.
- The Board ID (`board_id()`) is now determined by reading a set of
four GPIO pins (GPIO138 as MSB, GPIO137, GPIO136, GPIO135 as LSB)
and interpreting their states as a base-3 encoded value using
the `gpio_base3_value()` helper.
- The SKU ID (`sku_id()`) is retrieved from the Google ChromeEC
by calling `google_chromeec_get_board_sku()` when a ChromeEC
is configured (`CONFIG(EC_GOOGLE_CHROMEEC)`).
Both ID values are cached after their initial determination to
avoid redundant reads.
BUG=b:404985109
TEST=Able to build google/bluey
Change-Id: Ic5a084e35b33a82fef76f33c2663aba7a48c16a7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit updates the devicetree for the Google Bluey mainboard
to include entries for the WLAN and SSD PCI devices.
These devices are located on the x1p42100 SoC's PCI domain 0:
- WLAN: device pci 04.0
- SSD: device pci 06.0
BUG=b:404985109
TEST=Able to build google/bluey.
Change-Id: If0a9491f4178ee9a44c04aea1330b6522dfd9bf0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87859
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
