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mb/google/nissa/var/pujjoniru: Config AUX gpio to correct TCSS port

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In TWL, Type-C0 corresponds to TCSS port1, and Type-C1 corresponds
to TCSS port0. In order for the DP functions of the two Type-C ports
to operate normally, the corresponding relationship needs to be
configured correctly.

BUG=b:418106736
TEST=DP function of Type-C0/C1 workable

Change-Id: I4aa406e72d1e5f0434866b105f20df6362f3d304
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87899
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: hualin wei <weihualin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit is contained in:
Jianeng Ceng 2025-05-30 12:59:26 +08:00 • committed by Matt DeVillier
commit 0af68855c0
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/google/brya/variants/pujjoniru/overridetree.cb
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@ -27,12 +27,12 @@ chip soc/intel/alderlake
# motherboard to USBC connector
register "tcss_aux_ori" = "5"
register "typec_aux_bias_pads[0]" = "{
register "typec_aux_bias_pads[1]" = "{
.pad_auxp_dc = GPP_E22,
.pad_auxn_dc = GPP_E23
}"
register "typec_aux_bias_pads[1]" = "{
register "typec_aux_bias_pads[0]" = "{
.pad_auxp_dc = GPP_A21,
.pad_auxn_dc = GPP_A22
}"