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mb/google/trulo/var/pujjocento: Configure USB related settings

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Modify USB related settings according to the proto schematic diagram.

BUG=b:409254508
BRANCH=none
TEST=emerge-nissa coreboot chromeos-bootimage,tested USBA and TYPEC function is ok.

Change-Id: I48ec269b612602578b35eeaedffd1a3d311bb97e
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87834
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kun Liu 2025-05-26 10:09:44 +08:00 • committed by Subrata Banik
commit 3b68408693
1 changed files with 51 additions and 16 deletions
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67
src/mainboard/google/brya/variants/pujjocento/overridetree.cb
View file

@ -42,15 +42,15 @@ chip soc/intel/alderlake
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C MB (7.5 inch)
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C DB (7.1 inch)
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MB (6.4 inch)
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A DB (6.2 inch)
register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # Type-A MB (6.4 inch)
register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A DB (6.2 inch)
register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # LTE (3.3 inch)
register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # UFC (3.7 inch)
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN (2.5 inch)
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A0(MLB))
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A1(DB)
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3 Type-A port A0(MLB))
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB3 Type-A port A1(DB)
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WWAN(LTE)
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
@ -157,7 +157,6 @@ chip soc/intel/alderlake
}"
device domain 0 on
device ref igpu on end
device ref dtt on
chip drivers/intel/dptf
## sensor information
@ -323,6 +322,43 @@ chip soc/intel/alderlake
end
end
end
device ref igpu on
chip drivers/gfx/generic
register "device_count" = "4"
# DDIA for eDP
register "device[0].name" = ""LCD0""
# Internal panel on the first port of the graphics chip
register "device[0].type" = "panel"
# DDIB for HDMI
# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
register "device[1].name" = ""DD01""
# TCP0 (DP-1) for port C0
register "device[2].name" = ""DD02""
register "device[2].use_pld" = "true"
register "device[2].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
# TCP1 (DP-2) for port C1
register "device[3].name" = ""DD03""
register "device[3].use_pld" = "true"
register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
device generic 0 on end
end
end
device ref pmc hidden
chip drivers/intel/pmc_mux
device generic 0 on
chip drivers/intel/pmc_mux/conn
use usb2_port1 as usb2_port
use tcss_usb3_port1 as usb3_port
device generic 0 alias conn0 on end
end
chip drivers/intel/pmc_mux/conn
use usb2_port2 as usb2_port
use tcss_usb3_port2 as usb3_port
device generic 1 alias conn1 on end
end
end
end
end
device ref tcss_xhci on
chip drivers/usb/acpi
device ref tcss_root_hub on
@ -330,14 +366,14 @@ chip soc/intel/alderlake
register "desc" = ""USB3 Type-C Port C0 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
device ref tcss_usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C1 (MLB)""
register "desc" = ""USB3 Type-C Port C1 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
device ref tcss_usb3_port2 on end
end
end
@ -350,28 +386,28 @@ chip soc/intel/alderlake
register "desc" = ""USB2 Type-C Port C0 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
device ref usb2_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C1 (MLB)""
register "desc" = ""USB2 Type-C Port C1 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
device ref usb2_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A0 (MLB)""
register "type" = "UPC_TYPE_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))"
device ref usb2_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A1 (DB)""
register "type" = "UPC_TYPE_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, CENTER, ACPI_PLD_GROUP(4, 1))"
device ref usb2_port4 on end
end
chip drivers/usb/acpi
@ -406,14 +442,14 @@ chip soc/intel/alderlake
register "desc" = ""USB3 Type-A Port A0 (MLB)""
register "type" = "UPC_TYPE_USB3_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))"
device ref usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port A1 (DB)""
register "type" = "UPC_TYPE_USB3_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, CENTER, ACPI_PLD_GROUP(4, 1))"
device ref usb3_port2 on end
end
chip drivers/usb/acpi
@ -632,7 +668,6 @@ chip soc/intel/alderlake
device pnp 0c09.0 on end
end
end
device ref pmc hidden end
device ref hda on
chip drivers/sof
register "spkr_tplg" = "max98360a"