mb/google/ocelot/var/ocelot: Update initial overridetree settings
Update override devicetree based on schematic_1433518. BUG=b:394208231 TEST=Build Ocelot and verify it compiles without any error. Change-Id: I88a3729ff2a61a383a4715a335062310cba01f24 Signed-off-by: P, Usha <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
P, Usha
Nick Vaccaro
parent
4199351c1b
commit
b9754131a6
1 changed files with 58 additions and 104 deletions
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@ -61,32 +61,33 @@ end
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chip soc/intel/pantherlake
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
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register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
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register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C2
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register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C3
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register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port A0
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register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-A Port A1 / WWAN with rework
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register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type C port - various configurations - TCP0
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register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type C port - various configurations - TCP1
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register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # USB3.2 Gen2x1 Type-A Port - TAP1 Vertical CONN
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register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # USB3.2 Gen2x1 Type-A Port - TAP2 (redriver topology)
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register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # 2x5 USB2 HDR
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register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # 2x5 USB2 HDR
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register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # FPS
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register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # M.2 WLAN
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #1
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #2 / M.2 WWAN with rework
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB 3.2 Gen2 x1 Type-A Con - # 1
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB 3.2 Gen2 x1 Type-A Con - # 2 (redriver topology)
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#register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # TCSS Module - Type-A over TCP module
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register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
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register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)"
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register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
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register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
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register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
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register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN"
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register "tcss_cap_policy[1]" = "TCSS_TYPE_C_PORT_FULL_FUN"
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register "tcss_cap_policy[2]" = "TCSS_TYPE_C_PORT_FULL_FUN"
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register "tcss_cap_policy[3]" = "TCSS_TYPE_C_PORT_FULL_FUN"
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# Enable EDP in PortA
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# Enable EDP in PortA & HDMI in Port B
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register "ddi_port_A_config" = "1"
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register "ddi_port_B_config" = "1"
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register "ddi_ports_config" = "{
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[DDI_PORT_A] = DDI_ENABLE_HPD,
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}"
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[DDI_PORT_A] = DDI_ENABLE_HPD,
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[DDI_PORT_B] = DDI_ENABLE_HPD,
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}"
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register "serial_io_i2c_mode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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@ -107,10 +108,7 @@ chip soc/intel/pantherlake
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| I2C1 | Camera(CRD1) |
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#| I2C2 | Camera(CRD2) |
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#| I2C3 | Audio, TPM(cr50) |
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#| I2C4 | Touchscreen |
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#| I2C1 | TPM(cr50) |
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#| I2C5 | Touchpad |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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@ -118,12 +116,12 @@ chip soc/intel/pantherlake
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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.i2c[1] = {
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.speed = I2C_SPEED_FAST,
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.early_init = 1,
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},
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.i2c[2] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[3] = {
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.early_init = 1,
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.speed = I2C_SPEED_FAST,
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},
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.i2c[4] = {
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@ -412,31 +410,31 @@ chip soc/intel/pantherlake
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device ref usb2_port2 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C2""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "desc" = ""USB2 Type-A Port 1""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(3, 1)"
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device ref usb2_port3 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C3""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "desc" = ""USB2 Type-A Port 2""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(4, 1)"
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device ref usb2_port4 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port 1""
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register "desc" = ""USB2 Type-A Port 3""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(5, 1)"
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device ref usb2_port5 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port 2""
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register "desc" = ""USB2 Type-A Port 4""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(6, 1)"
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device ref usb2_port6 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port 3""
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register "desc" = ""USB2 Type-A Port 5""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(7, 1)"
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device ref usb2_port7 on end
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@ -444,7 +442,7 @@ chip soc/intel/pantherlake
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chip drivers/usb/acpi
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register "desc" = ""USB2 Bluetooth""
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register "type" = "UPC_TYPE_INTERNAL"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B09)"
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device ref usb2_port8 on
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probe WIFI WIFI_PCIE_6
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probe WIFI WIFI_PCIE_7
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@ -471,86 +469,41 @@ chip soc/intel/pantherlake
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probe STORAGE STORAGE_UNKNOWN
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end
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device ref pcie_rp2 on
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probe CELLULAR CELLULAR_PCIE
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register "pcie_rp[PCIE_RP(2)]" = "{
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.clk_src = 5,
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.clk_req = 5,
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.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
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}"
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chip soc/intel/common/block/pcie/rtd3
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D03)"
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register "reset_off_delay_ms" = "20"
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register "srcclk_pin" = "5"
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register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
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register "skip_on_off_support" = "true"
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register "use_rp_mutex" = "true"
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device generic 0 alias rp2_rtd3 on end
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end
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chip drivers/wwan/fm
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register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A09)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B20)"
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register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D03)"
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register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E02)"
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register "add_acpi_dma_property" = "true"
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use rp2_rtd3 as rtd3dev
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device generic 0 on end
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end
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end # WWAN
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device ref pcie_rp3 on
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probe SD SD_GENSYS
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probe SD SD_BAYHUB
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# Enable PCH PCIE x1 slot using CLK 3
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register "pcie_rp[PCIE_RP(3)]" = "{
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.clk_src = 2,
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.clk_req = 2,
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.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
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}"
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A08)"
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register "enable_delay_ms" = "100"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D19)"
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register "reset_delay_ms" = "20"
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register "srcclk_pin" = "2"
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device generic 0 on end
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end
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end # PCIE x1 slot
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device ref pcie_rp4 on
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probe WIFI WIFI_PCIE_6
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probe WIFI WIFI_PCIE_7
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register "pcie_rp[PCH_RP(4)]" = "{
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.clk_src = 4,
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.clk_req = 4,
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.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
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}"
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chip soc/intel/common/block/pcie/rtd3
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)"
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register "srcclk_pin" = "4"
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device pci 00.0 on end
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end
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chip drivers/wifi/generic
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register "add_acpi_dma_property" = "true"
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register "wake" = "GPE0_DW0_12" # GPP_A12
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use usb2_port7 as bluetooth_companion
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device pci 00.0 on end
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end
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end # discrete WLAN
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device ref pcie_rp5 on
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device ref pcie_rp1 on
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probe STORAGE STORAGE_NVME_GEN4
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probe STORAGE STORAGE_UNKNOWN
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register "pcie_rp[PCIE_RP(5)]" = "{
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.clk_src = 6,
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.clk_req = 6,
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register "pcie_rp[PCIE_RP(1)]" = "{
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.clk_src = 3,
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.clk_req = 3,
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.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
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}"
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chip soc/intel/common/block/pcie/rtd3
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register "is_storage" = "true"
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H18)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A08)"
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register "srcclk_pin" = "6"
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register "srcclk_pin" = "3"
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device generic 0 on end
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end
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end # Gen4 M.2 SSD
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device ref pcie_rp5 on
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probe SD SD_GENSYS
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probe SD SD_BAYHUB
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register "pcie_rp[PCIE_RP(5)]" = "{
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.clk_src = 2,
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.clk_req = 2,
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.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
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}"
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F10)"
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register "enable_delay_ms" = "100"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E03)"
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register "reset_delay_ms" = "20"
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register "srcclk_pin" = "2"
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device generic 0 on end
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end
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end # PCIE x1 slot
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device ref cnvi_wifi on
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probe WIFI WIFI_CNVI_6
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probe WIFI WIFI_CNVI_7
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@ -569,16 +522,17 @@ chip soc/intel/pantherlake
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end
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# NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.
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# TPM device is under i2c3. Therefore, i2c0 needs to be enabled anyways.
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# TPM device is under i2c1. Therefore, i2c0 needs to be enabled anyways.
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device ref i2c0 on end
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device ref i2c1 on end
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device ref i2c2 on end
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device ref i2c3 on
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device ref i2c1 on
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chip drivers/i2c/tpm
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register "hid" = ""GOOG0005""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D15_IRQ)"
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B17_IRQ)"
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device i2c 50 on end
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end
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end
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device ref i2c2 on end
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device ref i2c3 on
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end # I2C3
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device ref i2c4 off
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end # I2C4
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@ -588,7 +542,7 @@ chip soc/intel/pantherlake
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register "generic.desc" = ""Hynitron TOUCHPAD""
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register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F18_IRQ)"
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# NOTE: pmc_gpe0_dw0 will be overridden to GPP_F in variant.c.
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register "generic.wake" = "GPE0_DW0_18"
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register "generic.wake" = "GPE0_DW0_13"
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register "generic.uid" = "5"
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register "generic.detect" = "1"
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register "hid_desc_reg_offset" = "0x20"
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