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mb/google/nissa/var/pujjoniru: Update DTT settings for thermal control

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update DTT settings for thermal control, according to
b:395802079#comment37.

BUG=b:395802079
TEST=emerge-nissa coreboot

Change-Id: Ia3d27baf31f2ba684d3bd8f84e19ce802c3b68d1
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87545
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Qinghong Zeng 2025-05-06 15:24:57 +08:00 • committed by Eric Lai
commit f6926dc8a5
1 changed files with 6 additions and 6 deletions
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12
src/mainboard/google/brya/variants/pujjoniru/overridetree.cb
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@ -102,8 +102,8 @@ chip soc/intel/alderlake
}"
register "power_limits_config[ADL_N_081_15W_CORE]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 25,
.tdp_pl1_override = 22,
.tdp_pl2_override = 35,
.tdp_pl4 = 114,
}"
@ -279,15 +279,15 @@ chip soc/intel/alderlake
register "controls.power_limits" = "{
.pl1 = {
.min_power = 12000,
.max_power = 15000,
.min_power = 15000,
.max_power = 22000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200
},
.pl2 = {
.min_power = 25000,
.max_power = 25000,
.min_power = 35000,
.max_power = 35000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 1000