While I don't have +2 rights, I think it makes sense to add myself as
maintainer given I'm a creator of both ports in upstream tree.
Change-Id: I2484fc488040c2d86bbf3bf98f39354bf88efae8
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Add a check to make sure lsusb and lspci are installed, as the script
relies on them to function properly. Previously, if lsusb was not
installed, the script proceeded as if nothing was wrong, but never found
any devices plugged into the debug port. If lspci was not found, the
script exited saying that no EHCI debug capable controller was found.
The "command not found" messages that normally would have been shown in
these situations was not being shown, as stderr is redirected to
/dev/null to hide error messages that don't matter as per the comment
near the top of the script.
Change-Id: Ib56a20aab9552aa6321c2fb9ad0d2ca7d6cd00c7
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Commit ce10b6f821 unhid the BOOT0000
device from Windows. It requires a driver that's available from Coolstars EC bundle.
Guard this against the ChromeEC, so that non-Chromebooks don't get an
error device in Device Manager.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6645c1be7d602a2775f703f5cf56e4c9d6f3bb76
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Rather than unconditionally returning that the device is present,
return whether the fTPM is on or not.
Test=Boot the StarLite Mk V with the Intel ME disabled, and check
that the TPM is reported as not present.
Change-Id: If8236021bf0e1264646971cff9c998fac99ac220
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85228
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The CLFR method exists outside the CNVi device, so add `^` to allow
it to be found. This fixes the SSDT and allows the method to be used.
TEST=build/boot starlabs/starlite_adl
Change-Id: I1158cf1ccf50d9095fdab8d2d663041ef1985513
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The DPTF parameters were defined by the thermal team.
Based on thermal table in 377955793#comment20
BUG=b:377955793
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I0455d62a9f174fd911e5aa0b9626329ad2ac8f06
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86000
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
There is an issue where the codec enable signal is not working correctly
when FPS (Fingerprint Sensor) is enabled. This commit applies a
temporary workaround by using a dedicated GPIO pin for codec enable.
This allows the codec to function properly even when FPS is enabled,
preventing audio issues. A proper fix in hardware schematics will be
implemented in a future update.
BUG=b:390031369
TEST=Verified audio playback works with FPS being enabled.
Change-Id: I9883036b5e964cb55bd34c36398a501f69a8ecaa
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
The file chromeos-debug-fsp.fmd is no longer needed, as the FMD
configuration is now handled by the generic Chrome OS FMD file.
This change removes the file to simplify the build process and
reduce the amount of code that needs to be maintained.
Change-Id: Ida430d415ae3f7dc93b89eb4d7c7ba59ed280e1b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85971
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
dt_find_node() calls dt_read_cell_props() for every node it walks, but
this is only actually necessary when the caller is interested in the
`#address-cells` and `#size-cells` values and passed out-parameters to
receive them. Most callers don't actually do that, and we scan through
all properties needlessly on every node. This patch adds a fast path to
skip that.
Change-Id: I114f824a7d88b0bac4a96aca3f7dced459503b02
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85989
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This patch wraps `dt_find_node()` in a function that initializes the
addr_cells and size_cells values to the defaults provided in the FDT
specification before potentially updating them from found values, so
that we always return the correct result and remove the burden of
correctly initializing them from the caller.
Change-Id: I39ba2c82d3a0d0b39a2ed5eba2420a04fbccb2f7
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85988
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
In Flattened Device Trees, there exist special properties called
`#address-cells` and `#size-cells` that determine how large addresses
and sizes in `reg` properties are. According to the FDT specification,
each `reg` node cares about the `...cells` property in the _parent_ of
its node. Our current implementation looks for those properties in the
node it finds and returns, which would presumably be the node with the
`reg` property itself. Therefore, we're returning the wrong `...cells`
values.
This isn't really a problem in practice because we also allow inheriting
these properties from the parent when they don't exist in the child, and
nodes that contain `reg` properties usually don't contain `...cells`
properties themselves (because those properties would be incorrect and
useless there), so we usually just end up falling back to the (correct)
value we inherited from the parent. But it's still better to just fix
the mistake, and if we ever happen to have a situation where the node
containing the `reg` property still has children that require different
`...cells` values as well, it could make a difference. (The fact that
we're inheriting these properties is also technically incorrect
according to the spec, but we're doing that intentionally to match
behavior in the Linux kernel.)
This issue was already correctly implemented in the recently added
fdt_find_node() from commit 33079b8174 ("lib/device_tree: Add some FDT
helper functions"), and this patch also fixes it in the older
dt_find_node().
Change-Id: I323066477a4d4be17225e0915a81ce2ff39c1e40
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85964
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
mt6373_init_pmif_arb() needs to be initialized for SD card to control
the regulator.
TEST=emrege-rauru coreboot
TEST=The assertion is gone on Rauru during normal boot.
Change-Id: I7e3265bb62a6c78d44e2c756be9a020a49a03056
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85969
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Return to the caller immediately if pmif_arb has been initiailized. In
this way, we can skip unnecessary check and reduce the access to the
PMIF register.
TEST=emerge-geralt coreboot && emerge-rauru coreboot
Change-Id: Id1d11f8b238855edb393d77151159792e7716d22
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This has always been set in downstream defconfig's; remove it here
to avoid build issues with Jenkin's being unable to find a suitable
EC binary.
Change-Id: I02a10211d7cec9a2c8a0837f77ca17acdcb06c22
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add Kconfig options for `_SB`, the smart battery variant which
is identical apart from a different EC which supports a Smart
Battery instead of the CW2015.
Change-Id: I1e04ea26ef597ce542a7348982d056fb55de0d22
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The selected options were a bit illogical, so but them all under
the common board Kconfig, alphabetise and dedpulicate them.
Change-Id: I277249323e8735dda0a6e394e475435ddedf5537
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85972
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the Q-Events used by the merlin EC to their respective
files, i.e. `Q0B` for Battery Status Update to battery.asl.
This means that only revelant events will be included.
Change-Id: Ib41fbafd79b999409a520361a4d372902d878794
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85945
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As suggested by the linter:
Prefer 'unsigned long' over 'unsigned long int' as the int is unnecessary
Link: https://qa.coreboot.org/job/coreboot-untested-files/lastSuccessfulBuild/artifact/lint.txt
Change-Id: I7eddb0934ccd24c9994a60d7058a1e518c6c9c9f
Signed-off-by: Ariel Otilibili <otilibil@eurecom.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85785
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refactor GPIO programming to support UFS storage on the fatcat
platform.
- Add pad configurations for UFS in `fw_config.c`.
- Update `fw_config_configure_pre_mem_gpio()` and
`fw_config_gpio_padbased_override()` to include UFS support.
- Remove redundant UFS pad configuration from `gpio.c`.
TEST=Able to build and boot from UFS device on google/fatcat.
Change-Id: I09331d75501977d89592d1a70d5b0dca271f8747
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Skip UFC/WFC GPIO programming for power-on and clock configuration.
Clock configuration is now handled by native-function in ramstage,
and there is no need to power-on the camera module early in the boot
phase. Doing so resulted in the privacy LED being turned on during the
entire boot process, which is unnecessary.
BUG=b:381044394
TEST=No privacy LED blinking seen while booting google/fatcat.
Change-Id: Iae984a2ab6f797af450166c90f4a2c6d3e0e1caa
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85955
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD for camera devices to
prevent them from being probed during kernel boot.
This prevents the privacy LED from blinking unnecessarily.
Also includes minor code comment changes for clarity:
- Replace "560000000" with "560 * MHz" for readability.
- Explain `clknum` value `0` as `IMGCLKOUT_0` and `1` as `IMGCLKOUT_1`.
- Introduce FW_CONFIG (UFC/WFC) for probing IPU0.
BUG=b:381044394
TEST=No privacy LED blinking seen while rebooting google/fatcat.
Change-Id: I4712b751015d86d40dfd4d7da8cba956c435eef5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85954
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
TEST=Able to verify display using all the display end-point device.
Change-Id: I32f74411aa80279d63c3b12087ffc47b33fcc039
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85953
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces the missing PCI device IDs for Panther Lake
CNVi Bluetooth devices. These IDs are listed in document #815002 -
Panther Lake U/H Processor - External Design Specification Volume 1.
TEST=The CNVB device is now present in the ACPI SSDT table when the
cnvi_bluetooth device is enabled.
Change-Id: I45b42b0694d530763d4cd321aefc64141d088e2b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85959
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updates the structures to match the ones in the FSP.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I0603f5da689b6738ea54305a665b150121bc520c
Original-signed-off-by: Satya SreenivasL <satya.sreenivasl@amd.com>
Original-reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com>
Original-reviewed-by: Ritul Guru <ritul.bits@gmail.com>
Original-tested-by: Satya Sreenivas L <Satya.SreenivasL@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Glinda SoC PSP MBOX offset is 0x10970 & hence update the same in Kconfig
TEST=Tested with Birman Plus and it solved the issue for psp timeout
Before:
[DEBUG] PSP: Notify SMM info... error: PSP command timeout
After:
[DEBUG] PSP: Notify SMM info... OK
Change-Id: I328959513228fe0f9e78070eb6b302ef89857b42
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85627
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove variant directories for boards that haven't or won't be
ported, or that now use the common "Merlin" code.
Change-Id: Ibfdd858c6460a1291d6a15bb7eccee9e9006adff
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Refactor the FSP log level control by introducing a helper function
`fsp_set_debug_level()` to set the serial and MRC debug levels.
This change improves code readability and maintainability by separating
the log level setting logic from the main control flow. It also adds a
check to ensure the configured log levels are valid.
Change-Id: I6efd6a0ea006b4013dce1c8849b7dbbd4ea5e1dc
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85934
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
When battery is not present, reduce power limits,
avoid inability to enter the system.
This will check the current battery status and configure cpu power
limits using current PD power value.
BUG=b:384883899
BRANCH=none
TEST=built and verified PL4 values,power engineer verify pass.
Change-Id: I7e0c7289c20c4ce51eae2a48eb8f09acfcb9e958
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85894
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit streamlines the call to the
soc_read_core_scaling_factors() function. When runtime access to the
core scaling factors is not available, a static fallback is used based
on the CONFIG_SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR and
CONFIG_SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR options.
TEST=Successfully read performance and efficient scaling factors on a
fatcat board.
Change-Id: I62e903bea07f2981dfcbaf61d3b918e7c332afc5
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Suggested-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Refactor vendorcode MPIO configuration functions to be invoked from
the openSIL driver.
Change-Id: I8b1f92f08565216dd93203a06015e3eec1e7bb69
Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
According to the Intel emmc tuning results, we modify the relevant register values recommended in b:386317255/comment16 to ensure good emmc performance.
BUG=b:386317255
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: Ibdbb96f9623612a8eb5e01818859c4844ca4de13
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85933
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Modify Uldrenite ROM size from 16MB to 32MB.
BUG=b:388426787
TEST=emerge-nissa coreboot and check rom size is 32MB
Change-Id: I39f50415e093eb82342462f03cf50e89bce8cd93
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85932
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
