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mb/google/nissa/var/rull: eMMC DLL tuning

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According to the Intel emmc tuning results, we modify the relevant register values recommended in b:386317255/comment16 to ensure good emmc performance.

BUG=b:386317255
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: Ibdbb96f9623612a8eb5e01818859c4844ca4de13
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85933
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Rui Zhou 2025-01-10 15:38:52 +08:00 • committed by Subrata Banik
commit cf29b45866
1 changed files with 1 additions and 1 deletions
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src/mainboard/google/brya/variants/rull/overridetree.cb
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@ -58,7 +58,7 @@ chip soc/intel/alderlake
# 11: Reserved
# [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
# [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004C"
register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10023"
# EMMC Rx Strobe Delay
# Refer to EDS-Vol2-42.3.11.