drivers/amd/opensil/mpio: Factor out common MPIO symbols from vendorcode

Refactor vendorcode MPIO configuration functions to be invoked from
the openSIL driver.

Change-Id: I8b1f92f08565216dd93203a06015e3eec1e7bb69
Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/drivers/amd/opensil/Makefile.mk

@@ -2,6 +2,8 @@
 
 ifeq ($(CONFIG_OPENSIL_DRIVER),y)
 
+subdirs-y += mpio
+
 ramstage-y += ramstage.c
 
 endif

src/drivers/amd/opensil/mpio/Makefile.mk

@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-$(CONFIG_OPENSIL_DRIVER) += chip.c

src/drivers/amd/opensil/mpio/chip.c

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <vendorcode/amd/opensil/opensil.h>
+
+#include "chip.h"
+#include "../opensil.h"
+
+struct chip_operations drivers_amd_opensil_mpio_ops = {
+	.name = "AMD MPIO",
+};
+
+void configure_mpio(void)
+{
+	opensil_mpio_global_config();
+
+	/* Find all devices with this chip that are directly below the chip */
+	for (struct device *dev = &dev_root; dev; dev = dev->next)
+		if (dev->chip_ops == &drivers_amd_opensil_mpio_ops &&
+		    dev->chip_info != dev->upstream->dev->chip_info)
+			opensil_mpio_per_device_config(dev);
+}

src/drivers/amd/opensil/opensil.h

@@ -5,5 +5,7 @@
 
 /* Set up openSIL env and call TP1 */
 void amd_opensil_silicon_init(void);
+/* Set global and per-device MPIO configurations */
+void configure_mpio(void);
 
 #endif /* OPENSIL_DRIVER_H */

src/drivers/amd/opensil/ramstage.c

@@ -3,11 +3,13 @@
 #include <bootstate.h>
 #include <vendorcode/amd/opensil/opensil.h>
 
+#include "mpio/chip.h"
 #include "opensil.h"
 
 void amd_opensil_silicon_init(void)
 {
 	setup_opensil();
+	configure_mpio();
 	opensil_xSIM_timepoint_1();
 }
 

src/mainboard/amd/birman/devicetree_phoenix_opensil.cb

@@ -208,7 +208,7 @@ chip soc/amd/phoenix
 
 	device domain 0 on
 		device ref iommu on end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "0"
 			register "end_lane" = "7"
@@ -217,7 +217,7 @@ chip soc/amd/phoenix
 			# register "gpio_group" is currently not used
 			device ref gpp_bridge_1_1 on end # MXM
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "8"
 			register "end_lane" = "11"
@@ -231,7 +231,7 @@ chip soc/amd/phoenix
 				end
 			end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "12"
 			register "end_lane" = "12"
@@ -239,7 +239,7 @@ chip soc/amd/phoenix
 			register "clk_req" = "CLK_REQ6"
 			device ref gpp_bridge_1_3 on end # GBE
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "13"
 			register "end_lane" = "13"
@@ -247,7 +247,7 @@ chip soc/amd/phoenix
 			register "clk_req" = "CLK_REQ5"
 			device ref gpp_bridge_2_1 on end # SD
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "14"
 			register "end_lane" = "14"
@@ -255,7 +255,7 @@ chip soc/amd/phoenix
 			register "clk_req" = "CLK_REQ4"
 			device ref gpp_bridge_2_2 on end # WWAN
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "15"
 			register "end_lane" = "15"
@@ -263,7 +263,7 @@ chip soc/amd/phoenix
 			register "clk_req" = "CLK_REQ3"
 			device ref gpp_bridge_2_3 on end # WIFI
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "16"
 			register "end_lane" = "19"

src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c

@@ -4,7 +4,7 @@
 #include <soc/amd/phoenix/chip.h>
 #include <soc/soc_util.h>
 #include <static.h>
-#include <vendorcode/amd/opensil/chip/mpio/chip.h>
+#include <drivers/amd/opensil/mpio/chip.h>
 #include "display_card_type.h"
 #include "update_devicetree.h"
 
@@ -14,10 +14,10 @@ static void mainboard_update_mpio(void)
 	struct device *ssd1_bridge = DEV_PTR(gpp_bridge_1_2);
 	struct device *wwan_bridge = DEV_PTR(gpp_bridge_2_2);
 	struct device *wlan_bridge = DEV_PTR(gpp_bridge_2_3);
-	struct vendorcode_amd_opensil_chip_mpio_config *mxm_bridge_cfg = config_of(mxm_bridge);
-	struct vendorcode_amd_opensil_chip_mpio_config *ssd1_bridge_cfg = config_of(ssd1_bridge);
-	struct vendorcode_amd_opensil_chip_mpio_config *wwan_bridge_cfg = config_of(wwan_bridge);
-	struct vendorcode_amd_opensil_chip_mpio_config *wlan_bridge_cfg = config_of(wlan_bridge);
+	struct drivers_amd_opensil_mpio_config *mxm_bridge_cfg = config_of(mxm_bridge);
+	struct drivers_amd_opensil_mpio_config *ssd1_bridge_cfg = config_of(ssd1_bridge);
+	struct drivers_amd_opensil_mpio_config *wwan_bridge_cfg = config_of(wwan_bridge);
+	struct drivers_amd_opensil_mpio_config *wlan_bridge_cfg = config_of(wlan_bridge);
 
 	/* Phoenix 2 has less PCIe lanes than Phoenix */
 	if (get_soc_type() == SOC_PHOENIX2) {

src/mainboard/amd/onyx_poc/devicetree.cb

@@ -55,7 +55,7 @@ chip soc/amd/genoa_poc
 	device domain 0 on
 		device ref iommu_0 on end
 		device ref rcec_0 on end
-		chip vendorcode/amd/opensil/chip/mpio # P2
+		chip drivers/amd/opensil/mpio # P2
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "48"
 			register "end_lane" = "63"
@@ -63,7 +63,7 @@ chip soc/amd/genoa_poc
 			register "aspm" = "L1"
 			device ref gpp_bridge_0_0_a on end
 		end
-		chip vendorcode/amd/opensil/chip/mpio # G2
+		chip drivers/amd/opensil/mpio # G2
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "112"
 			register "end_lane" = "127"
@@ -72,7 +72,7 @@ chip soc/amd/genoa_poc
 			register "hotplug" = "ServerExpress"
 			device ref gpp_bridge_0_0_b on end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "128"
 			register "end_lane" = "131"
@@ -93,7 +93,7 @@ chip soc/amd/genoa_poc
 	device domain 1 on
 		device ref iommu_1 on end
 		device ref rcec_1 on end
-		chip vendorcode/amd/opensil/chip/mpio # P3
+		chip drivers/amd/opensil/mpio # P3
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "16"
 			register "end_lane" = "31"
@@ -101,7 +101,7 @@ chip soc/amd/genoa_poc
 			register "aspm" = "L1"
 			device ref gpp_bridge_1_0_a on end
 		end
-		chip vendorcode/amd/opensil/chip/mpio # G3
+		chip drivers/amd/opensil/mpio # G3
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "80"
 			register "end_lane" = "95"
@@ -114,7 +114,7 @@ chip soc/amd/genoa_poc
 	device domain 2 on
 		device ref iommu_2 on end
 		device ref rcec_2 on end
-		chip vendorcode/amd/opensil/chip/mpio # P1
+		chip drivers/amd/opensil/mpio # P1
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "32"
 			register "end_lane" = "47"
@@ -123,7 +123,7 @@ chip soc/amd/genoa_poc
 			register "hotplug" = "ServerExpress"
 			device ref gpp_bridge_2_0_a on end
 		end
-		chip vendorcode/amd/opensil/chip/mpio # G1
+		chip drivers/amd/opensil/mpio # G1
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "64"
 			register "end_lane" = "79"
@@ -137,7 +137,7 @@ chip soc/amd/genoa_poc
 	device domain 3 on
 		device ref iommu_3 on end
 		device ref rcec_3 on end
-		chip vendorcode/amd/opensil/chip/mpio # P0
+		chip drivers/amd/opensil/mpio # P0
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "0"
 			register "end_lane" = "15"
@@ -145,7 +145,7 @@ chip soc/amd/genoa_poc
 			register "aspm" = "L1"
 			device ref gpp_bridge_3_0_a on end
 		end
-		chip vendorcode/amd/opensil/chip/mpio # G0
+		chip drivers/amd/opensil/mpio # G0
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "96"
 			register "end_lane" = "111"
@@ -153,7 +153,7 @@ chip soc/amd/genoa_poc
 			register "aspm" = "L1"
 			device ref gpp_bridge_3_0_b on end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "132"
 			register "end_lane" = "133"
@@ -161,7 +161,7 @@ chip soc/amd/genoa_poc
 			register "aspm" = "L1"
 			device ref gpp_bridge_3_0_c on end # WAFL
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "134"
 			register "end_lane" = "134"
@@ -170,7 +170,7 @@ chip soc/amd/genoa_poc
 			register "bmc" = "1"
 			device ref gpp_bridge_3_1_c on end # BMC
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "135"
 			register "end_lane" = "135"

src/soc/amd/genoa_poc/chipset.cb

@@ -16,78 +16,78 @@ chip soc/amd/genoa_poc
 		device pci 00.3 alias rcec_0 off end
 
 		device pci 01.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.1 alias gpp_bridge_0_0_a off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.2 alias gpp_bridge_0_1_a off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.3 alias gpp_bridge_0_2_a off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.4 alias gpp_bridge_0_3_a off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.5 alias gpp_bridge_0_4_a off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.6 alias gpp_bridge_0_5_a off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.7 alias gpp_bridge_0_6_a off end
 		end
 
 		device pci 02.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 02.1 alias gpp_bridge_0_7_a off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 02.2 alias gpp_bridge_0_8_a off end
 		end
 
 		device pci 03.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 03.1 alias gpp_bridge_0_0_b off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 03.2 alias gpp_bridge_0_1_b off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 03.3 alias gpp_bridge_0_2_b off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 03.4 alias gpp_bridge_0_3_b off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 03.5 alias gpp_bridge_0_4_b off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 03.6 alias gpp_bridge_0_5_b off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 03.7 alias gpp_bridge_0_6_b off end
 		end
 
 		device pci 04.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 04.1 alias gpp_bridge_0_7_b off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 04.2 alias gpp_bridge_0_8_b off end
 		end
 
 		device pci 05.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 05.1 alias gpp_bridge_0_0_c off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 05.2 alias gpp_bridge_0_1_c off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 05.3 alias gpp_bridge_0_2_c off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 05.4 alias gpp_bridge_0_3_c off end
 		end
 
@@ -128,64 +128,64 @@ chip soc/amd/genoa_poc
 		device pci 00.3 alias rcec_1 off end
 
 		device pci 01.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.1 alias gpp_bridge_1_0_a off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.2 alias gpp_bridge_1_1_a off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.3 alias gpp_bridge_1_2_a off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.4 alias gpp_bridge_1_3_a off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.5 alias gpp_bridge_1_4_a off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.6 alias gpp_bridge_1_5_a off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.7 alias gpp_bridge_1_6_a off end
 		end
 
 		device pci 02.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 02.1 alias gpp_bridge_1_7_a off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 02.2 alias gpp_bridge_1_8_a off end
 		end
 
 		device pci 03.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 03.1 alias gpp_bridge_1_0_b off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 03.2 alias gpp_bridge_1_1_b off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 03.3 alias gpp_bridge_1_2_b off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 03.4 alias gpp_bridge_1_3_b off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 03.5 alias gpp_bridge_1_4_b off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 03.6 alias gpp_bridge_1_5_b off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 03.7 alias gpp_bridge_1_6_b off end
 		end
 
 		device pci 04.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 04.1 alias gpp_bridge_1_7_b off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 04.2 alias gpp_bridge_1_8_b off end
 		end
 
@@ -207,64 +207,64 @@ chip soc/amd/genoa_poc
 		device pci 00.3 alias rcec_2 off end
 
 		device pci 01.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.1 alias gpp_bridge_2_0_a off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.2 alias gpp_bridge_2_1_a off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.3 alias gpp_bridge_2_2_a off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.4 alias gpp_bridge_2_3_a off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.5 alias gpp_bridge_2_4_a off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.6 alias gpp_bridge_2_5_a off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.7 alias gpp_bridge_2_6_a off end
 		end
 
 		device pci 02.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 02.1 alias gpp_bridge_2_7_a off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 02.2 alias gpp_bridge_2_8_a off end
 		end
 
 		device pci 03.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 03.1 alias gpp_bridge_2_0_b off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 03.2 alias gpp_bridge_2_1_b off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 03.3 alias gpp_bridge_2_2_b off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 03.4 alias gpp_bridge_2_3_b off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 03.5 alias gpp_bridge_2_4_b off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 03.6 alias gpp_bridge_2_5_b off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 03.7 alias gpp_bridge_2_6_b off end
 		end
 
 		device pci 04.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 04.1 alias gpp_bridge_2_7_b off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 04.2 alias gpp_bridge_2_8_b off end
 		end
 
@@ -286,78 +286,78 @@ chip soc/amd/genoa_poc
 		device pci 00.3 alias rcec_3 off end
 
 		device pci 01.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.1 alias gpp_bridge_3_0_a off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.2 alias gpp_bridge_3_1_a off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.3 alias gpp_bridge_3_2_a off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.4 alias gpp_bridge_3_3_a off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.5 alias gpp_bridge_3_4_a off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.6 alias gpp_bridge_3_5_a off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.7 alias gpp_bridge_3_6_a off end
 		end
 
 		device pci 02.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 02.1 alias gpp_bridge_3_7_a off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 02.2 alias gpp_bridge_3_8_a off end
 		end
 
 		device pci 03.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 03.1 alias gpp_bridge_3_0_b off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 03.2 alias gpp_bridge_3_1_b off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 03.3 alias gpp_bridge_3_2_b off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 03.4 alias gpp_bridge_3_3_b off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 03.5 alias gpp_bridge_3_4_b off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 03.6 alias gpp_bridge_3_5_b off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 03.7 alias gpp_bridge_3_6_b off end
 		end
 
 		device pci 04.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 04.1 alias gpp_bridge_3_7_b off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 04.2 alias gpp_bridge_3_8_b off end
 		end
 
 		device pci 05.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 05.1 alias gpp_bridge_3_0_c off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 05.2 alias gpp_bridge_3_1_c off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 05.3 alias gpp_bridge_3_2_c off end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 05.4 alias gpp_bridge_3_3_c off end
 		end
 

src/soc/amd/phoenix/chipset_opensil.cb

@@ -9,37 +9,37 @@ chip soc/amd/phoenix
 
 		device pci 01.0 on end # Dummy device function, do not disable
 		# The PCIe GPP aliases in this SoC match the device and function numbers
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.1 alias gpp_bridge_1_1 hidden ops amd_external_pcie_gpp_ops end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.2 alias gpp_bridge_1_2 hidden ops amd_external_pcie_gpp_ops end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.3 alias gpp_bridge_1_3 hidden ops amd_external_pcie_gpp_ops end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 01.4 alias gpp_bridge_1_4 hidden ops amd_external_pcie_gpp_ops end
 		end
 
 		device pci 02.0 on end # Dummy device function, do not disable
 		# The PCIe GPP aliases in this SoC match the device and function numbers
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 02.1 alias gpp_bridge_2_1 hidden ops amd_external_pcie_gpp_ops end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 02.2 alias gpp_bridge_2_2 hidden ops amd_external_pcie_gpp_ops end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 02.3 alias gpp_bridge_2_3 hidden ops amd_external_pcie_gpp_ops end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 02.4 alias gpp_bridge_2_4 hidden ops amd_external_pcie_gpp_ops end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 02.5 alias gpp_bridge_2_5 hidden ops amd_external_pcie_gpp_ops end
 		end
-		chip vendorcode/amd/opensil/chip/mpio
+		chip drivers/amd/opensil/mpio
 			device pci 02.6 alias gpp_bridge_2_6 hidden ops amd_external_pcie_gpp_ops end
 		end
 

src/vendorcode/amd/opensil/Kconfig

@@ -25,8 +25,8 @@ config AMD_OPENSIL_PATH
 
 config AMD_OPENSIL_MPIO_CHIP_H_FILE
 	string "Location of specific MPIO chip.h implementation"
-	default "../../genoa_poc/mpio/chip.h" if SOC_AMD_OPENSIL_GENOA_POC
-	default "../../stub/mpio/chip.h"
+	default "$(top)/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h" if SOC_AMD_OPENSIL_GENOA_POC
+	default "$(top)/src/vendorcode/amd/opensil/stub/mpio/chip.h"
 	help
 	  Set to the location of the MPIO chip.h in the selected openSIL
 	  implementation, so that the common MPIO chip.h file can include the

src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c

@@ -1,37 +1,19 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <RcMgr/DfX/RcManager4-api.h>
-#include <NBIO/NbioClass-api.h>
-#include <Mpio/MpioClass-api.h>
-#include <Mpio/Common/MpioStructs.h>
 #include <device/device.h>
 #include <device/pci_def.h>
+#include <Mpio/Common/MpioStructs.h>
+#include <Mpio/MpioClass-api.h>
+#include <NBIO/NbioClass-api.h>
+#include <RcMgr/DfX/RcManager4-api.h>
+#include <vendorcode/amd/opensil/opensil.h>
+#include <xSIM-api.h>
+
 #include "chip.h"
-#include "../../opensil.h"
 
-struct chip_operations vendorcode_amd_opensil_chip_mpio_ops = {
-	.name = "AMD GENOA MPIO",
-};
-
-static void nbio_config(void)
-{
-	NBIOCLASS_DATA_BLOCK *nbio_data = SilFindStructure(SilId_NbioClass, 0);
-	NBIOCLASS_INPUT_BLK *input = &nbio_data->NbioInputBlk;
-	input->CfgHdAudioEnable           = false;
-	input->EsmEnableAllRootPorts      = false;
-	input->EsmTargetSpeed             = 16;
-	input->CfgRxMarginPersistenceMode = 1;
-	input->CfgDxioFrequencyVetting    = false;
-	input->CfgSkipPspMessage          = 1;
-	input->CfgEarlyTrainTwoPcieLinks  = false;
-	input->EarlyBmcLinkTraining       = true;
-	input->EdpcEnable                 = 0;
-	input->PcieAerReportMechanism     = 2;
-	input->SevSnpSupport              = false;
-}
-
-static void mpio_global_config(MPIOCLASS_INPUT_BLK *mpio_data)
+static void mpio_params_config(void)
 {
+	MPIOCLASS_INPUT_BLK *mpio_data = SilFindStructure(SilId_MpioClass, 0);
 	mpio_data->CfgDxioClockGating                  = 1;
 	mpio_data->PcieDxioTimingControlEnable         = 0;
 	mpio_data->PCIELinkReceiverDetectionPolling    = 0;
@@ -104,7 +86,23 @@ static void mpio_global_config(MPIOCLASS_INPUT_BLK *mpio_data)
 	/* TODO handle this differently on multisocket */
 	mpio_data->PcieTopologyData.PlatformData[0].Flags = DESCRIPTOR_TERMINATE_LIST;
 	mpio_data->PcieTopologyData.PlatformData[0].PciePortList = mpio_data->PcieTopologyData.PortList;
+}
 
+static void nbio_params_config(void)
+{
+	NBIOCLASS_DATA_BLOCK *nbio_data = SilFindStructure(SilId_NbioClass, 0);
+	NBIOCLASS_INPUT_BLK *input = &nbio_data->NbioInputBlk;
+	input->CfgHdAudioEnable           = false;
+	input->EsmEnableAllRootPorts      = false;
+	input->EsmTargetSpeed             = 16;
+	input->CfgRxMarginPersistenceMode = 1;
+	input->CfgDxioFrequencyVetting    = false;
+	input->CfgSkipPspMessage          = 1;
+	input->CfgEarlyTrainTwoPcieLinks  = false;
+	input->EarlyBmcLinkTraining       = true;
+	input->EdpcEnable                 = 0;
+	input->PcieAerReportMechanism     = 2;
+	input->SevSnpSupport              = false;
 }
 
 static void setup_bmc_lanes(uint8_t lane, uint8_t socket)
@@ -125,12 +123,18 @@ static void setup_bmc_lanes(uint8_t lane, uint8_t socket)
 	mpio_data->EarlyBmcLinkDie                     = 0;
 }
 
-static void per_device_config(MPIOCLASS_INPUT_BLK *mpio_data, struct device *dev)
+void opensil_mpio_per_device_config(struct device *dev)
 {
+	/* Cache *mpio_data from SilFindStructure */
+	static MPIOCLASS_INPUT_BLK *mpio_data = NULL;
+	if (mpio_data == NULL) {
+		mpio_data = SilFindStructure(SilId_MpioClass, 0);
+	}
+
 	static uint32_t slot_num;
 	const uint32_t domain = dev_get_domain_id(dev);
 	const uint32_t devfn = dev->path.pci.devfn;
-	const struct vendorcode_amd_opensil_chip_mpio_config *const config = dev->chip_info;
+	const struct drivers_amd_opensil_mpio_config *const config = dev->chip_info;
 	printk(BIOS_DEBUG, "Setting MPIO port for domain 0x%x, PCI %d:%d\n",
 	       domain, PCI_SLOT(devfn), PCI_FUNC(devfn));
 
@@ -191,15 +195,8 @@ static void per_device_config(MPIOCLASS_INPUT_BLK *mpio_data, struct device *dev
 	mpio_port++;
 }
 
-void configure_mpio(void)
+void opensil_mpio_global_config(void)
 {
-	MPIOCLASS_INPUT_BLK *mpio_data = SilFindStructure(SilId_MpioClass, 0);
-	mpio_global_config(mpio_data);
-	nbio_config();
-
-	/* Find all devices with this chip that are directly below the chip */
-	for (struct device *dev = &dev_root; dev; dev = dev->next)
-		if (dev->chip_ops == &vendorcode_amd_opensil_chip_mpio_ops &&
-		    dev->chip_info != dev->upstream->dev->chip_info)
-			per_device_config(mpio_data, dev);
+	mpio_params_config();
+	nbio_params_config();
 }

src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h

@@ -54,7 +54,7 @@ enum pcie_aspm {
 	L0sL1,
 };
 
-struct vendorcode_amd_opensil_chip_mpio_config {
+struct drivers_amd_opensil_mpio_config {
 	enum mpio_type type;
 	uint8_t start_lane;
 	uint8_t end_lane;

src/vendorcode/amd/opensil/genoa_poc/ramstage.c

@@ -12,6 +12,7 @@
 #include <static.h>
 #include <stdio.h>
 #include <xSIM-api.h>
+
 #include "opensil_console.h"
 #include "../opensil.h"
 
@@ -128,7 +129,6 @@ void setup_opensil(void)
 	setup_rc_manager_default();
 	configure_usb();
 	configure_sata();
-	configure_mpio();
 }
 
 static void opensil_entry(SIL_TIMEPOINT timepoint)

src/vendorcode/amd/opensil/opensil.h

@@ -12,11 +12,12 @@ void add_opensil_memmap(struct device *dev, unsigned long *idx);
 // Fill in FADT from openSIL
 void opensil_fill_fadt_io_ports(acpi_fadt_t *fadt);
 
-void configure_mpio(void);
-
 void setup_opensil(void);
 void opensil_xSIM_timepoint_1(void);
 void opensil_xSIM_timepoint_2(void);
 void opensil_xSIM_timepoint_3(void);
 
+void opensil_mpio_global_config(void);
+void opensil_mpio_per_device_config(struct device *dev);
+
 #endif

src/vendorcode/amd/opensil/stub/mpio/chip.c

@@ -1,8 +1,16 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/device.h>
+#include <vendorcode/amd/opensil/opensil.h>
+
 #include "chip.h"
 
-struct chip_operations vendorcode_amd_opensil_chip_mpio_ops = {
-	.name = "AMD openSIL stub MPIO",
-};
+void opensil_mpio_global_config(void)
+{
+	printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__);
+}
+
+void opensil_mpio_per_device_config(struct device *dev)
+{
+	printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__);
+}

src/vendorcode/amd/opensil/stub/mpio/chip.h

@@ -60,7 +60,7 @@ enum pcie_slot_power_limit_scale {
 	SLOT_POWER_LIMIT_DIVISOR_1000 = 3,	/* Scale factor 0.001 */
 };
 
-struct vendorcode_amd_opensil_chip_mpio_config {
+struct drivers_amd_opensil_mpio_config {
 	enum mpio_engine_type type;
 	uint8_t start_lane;
 	uint8_t end_lane;