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mb/amd/birman_plus/devicetree_glinda.cb: Update USB

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Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Iacf9ab43c337a8b6a7aa5a37eb8a59644fcaeac6
Original-signed-off-by: Satya SreenivasL <satya.sreenivasl@amd.com>
Original-reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com>
Original-reviewed-by: Ritul Guru <ritul.bits@gmail.com>
Original-tested-by: Satya Sreenivas L <Satya.SreenivasL@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ana Carolina Cabral
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Maximilian Brune 2024-09-20 13:35:08 +02:00 • committed by Felix Held
commit 9ec24b648b
1 changed files with 58 additions and 29 deletions
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87
src/mainboard/amd/birman_plus/devicetree_glinda.cb
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@ -44,13 +44,13 @@ chip soc/amd/glinda
register "usb_phy_custom" = "1"
register "usb_phy" = "{
.Usb2PhyPort[0] = {
.compdistune = 0x3,
.compdistune = 0x1,
.pllbtune = 0x1,
.pllitune = 0x0,
.pllptune = 0xe,
.sqrxtune = 0x3,
.txfslstune = 0x3,
.txpreempamptune = 0x2,
.pllptune = 0xc,
.sqrxtune = 0x2,
.txfslstune = 0x1,
.txpreempamptune = 0x3,
.txpreemppulsetune = 0x0,
.txrisetune = 0x1,
.txvreftune = 0x3,
@ -58,13 +58,13 @@ chip soc/amd/glinda
.txrestune = 0x2,
},
.Usb2PhyPort[1] = {
.compdistune = 0x3,
.compdistune = 0x1,
.pllbtune = 0x1,
.pllitune = 0x0,
.pllptune = 0xe,
.sqrxtune = 0x3,
.txfslstune = 0x3,
.txpreempamptune = 0x2,
.pllptune = 0xc,
.sqrxtune = 0x2,
.txfslstune = 0x1,
.txpreempamptune = 0x3,
.txpreemppulsetune = 0x0,
.txrisetune = 0x1,
.txvreftune = 0x3,
@ -72,13 +72,13 @@ chip soc/amd/glinda
.txrestune = 0x2,
},
.Usb2PhyPort[2] = {
.compdistune = 0x3,
.compdistune = 0x1,
.pllbtune = 0x1,
.pllitune = 0x0,
.pllptune = 0xe,
.sqrxtune = 0x3,
.txfslstune = 0x3,
.txpreempamptune = 0x2,
.pllptune = 0xc,
.sqrxtune = 0x2,
.txfslstune = 0x1,
.txpreempamptune = 0x3,
.txpreemppulsetune = 0x0,
.txrisetune = 0x1,
.txvreftune = 0x3,
@ -86,13 +86,13 @@ chip soc/amd/glinda
.txrestune = 0x2,
},
.Usb2PhyPort[3] = {
.compdistune = 0x3,
.compdistune = 0x1,
.pllbtune = 0x1,
.pllitune = 0x0,
.pllptune = 0xe,
.sqrxtune = 0x3,
.txfslstune = 0x3,
.txpreempamptune = 0x2,
.pllptune = 0xc,
.sqrxtune = 0x2,
.txfslstune = 0x1,
.txpreempamptune = 0x3,
.txpreemppulsetune = 0x0,
.txrisetune = 0x1,
.txvreftune = 0x3,
@ -100,13 +100,13 @@ chip soc/amd/glinda
.txrestune = 0x2,
},
.Usb2PhyPort[4] = {
.compdistune = 0x3,
.compdistune = 0x1,
.pllbtune = 0x1,
.pllitune = 0x0,
.pllptune = 0xe,
.sqrxtune = 0x3,
.txfslstune = 0x3,
.txpreempamptune = 0x2,
.pllptune = 0xc,
.sqrxtune = 0x2,
.txfslstune = 0x1,
.txpreempamptune = 0x3,
.txpreemppulsetune = 0x0,
.txrisetune = 0x1,
.txvreftune = 0x3,
@ -114,13 +114,41 @@ chip soc/amd/glinda
.txrestune = 0x2,
},
.Usb2PhyPort[5] = {
.compdistune = 0x1,
.pllbtune = 0x1,
.pllitune = 0x0,
.pllptune = 0xc,
.sqrxtune = 0x2,
.txfslstune = 0x1,
.txpreempamptune = 0x3,
.txpreemppulsetune = 0x0,
.txrisetune = 0x1,
.txvreftune = 0x3,
.txhsxvtune = 0x3,
.txrestune = 0x2,
},
.Usb2PhyPort[6] = {
.compdistune = 0x3,
.pllbtune = 0x1,
.pllitune = 0x0,
.pllptune = 0xe,
.sqrxtune = 0x3,
.txfslstune = 0x3,
.txpreempamptune = 0x2,
.pllptune = 0xc,
.sqrxtune = 0x2,
.txfslstune = 0x1,
.txpreempamptune = 0x3,
.txpreemppulsetune = 0x0,
.txrisetune = 0x1,
.txvreftune = 0x3,
.txhsxvtune = 0x3,
.txrestune = 0x2,
},
.Usb2PhyPort[7] = {
.compdistune = 0x3,
.pllbtune = 0x1,
.pllitune = 0x0,
.pllptune = 0xc,
.sqrxtune = 0x2,
.txfslstune = 0x1,
.txpreempamptune = 0x3,
.txpreemppulsetune = 0x0,
.txrisetune = 0x1,
.txvreftune = 0x3,
@ -147,6 +175,7 @@ chip soc/amd/glinda
},
.ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C,
.ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C,
.ComboPhyStaticConfig[2] = USB_COMBO_PHY_MODE_USB_C,
}"
register "gpp_clk_config[0]" = "GPP_CLK_REQ"