mb/starlabs/byte_adl: Put options in CFR cbtable
Change-Id: I11349397e41fb2c7a3f26ab172a2c4b30d24bc0a Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85710 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Sean Rhodes
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d0ce8d8146
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02f31d080c
4 changed files with 216 additions and 47 deletions
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@ -1,9 +1,10 @@
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config BOARD_STARLABS_BYTE_SERIES
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def_bool n
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select DRIVERS_EFI_VARIABLE_STORE
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select DRIVERS_OPTION_CFR
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select EC_STARLABS_ITE
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_CMOS_DEFAULT
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select HAVE_OPTION_TABLE
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select INTEL_GMA_HAVE_VBT
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select INTEL_LPSS_UART_FOR_CONSOLE
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214
src/mainboard/starlabs/byte_adl/cfr.c
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214
src/mainboard/starlabs/byte_adl/cfr.c
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@ -0,0 +1,214 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <boot/coreboot_tables.h>
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#include <commonlib/coreboot_tables.h>
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#include <drivers/option/cfr_frontend.h>
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#include <inttypes.h>
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#include <intelblocks/pcie_rp.h>
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#include <string.h>
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#include <types.h>
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#include <variants.h>
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static const struct sm_object boot_option = SM_DECLARE_ENUM({
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.opt_name = "boot_option",
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.ui_name = "Boot Option",
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.ui_helptext = "Change the boot device in the event of a failed boot",
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.default_value = 0,
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.values = (const struct sm_enum_value[]) {
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{ "Fallback", 0 },
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{ "Normal", 1 },
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SM_ENUM_VALUE_END },
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});
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static const struct sm_object debug_level = SM_DECLARE_ENUM({
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.opt_name = "debug_level",
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.ui_name = "Debug Level",
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.ui_helptext = "Set the verbosity of the debug output.",
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.default_value = 0,
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.values = (const struct sm_enum_value[]) {
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{ "Emergency", 0 },
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{ "Alert", 1 },
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{ "Critical", 2 },
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{ "Error", 3 },
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{ "Warning", 4 },
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{ "Notice", 5 },
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{ "Info", 6 },
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{ "Debug", 7 },
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{ "Spew", 8 },
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SM_ENUM_VALUE_END },
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});
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#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE)
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static const struct sm_object gna = SM_DECLARE_BOOL({
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.opt_name = "gna",
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.ui_name = "Gaussian & Neural Accelerator",
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.ui_helptext = "Enable or Disable the Gaussian & Neural Accelerator",
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.default_value = false,
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});
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#endif
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static const struct sm_object me_state = SM_DECLARE_ENUM({
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.opt_name = "me_state",
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.ui_name = "Intel Management Engine",
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.ui_helptext = "Enable or disable the Intel Management Engine",
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.default_value = 1,
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.values = (const struct sm_enum_value[]) {
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{ "Disabled", 1 },
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{ "Enabled", 0 },
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SM_ENUM_VALUE_END },
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});
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static const struct sm_object me_state_counter = SM_DECLARE_NUMBER({
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.opt_name = "me_state_counter",
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.ui_name = "ME State Counter",
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.flags = CFR_OPTFLAG_SUPPRESS,
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.default_value = 0,
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});
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static const struct sm_object power_on_after_fail = SM_DECLARE_BOOL({
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.opt_name = "power_on_after_fail",
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.ui_name = "Power on after failure",
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.ui_helptext = "Automatically turn on after a power failure",
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.default_value = false,
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});
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static const struct sm_object power_profile = SM_DECLARE_ENUM({
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.opt_name = "power_profile",
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.ui_name = "Power Profile",
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.ui_helptext = "Select whether to maximize performance, battery life or both.",
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.default_value = 1,
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.values = (const struct sm_enum_value[]) {
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{ "Power Saver", PP_POWER_SAVER },
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{ "Balanced", PP_BALANCED },
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{ "Performance", PP_PERFORMANCE },
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SM_ENUM_VALUE_END },
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});
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#if CONFIG(SOC_INTEL_ALDERLAKE)
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static const struct sm_object pciexp_aspm = SM_DECLARE_ENUM({
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.opt_name = "pciexp_aspm",
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.ui_name = "PCI ASPM",
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.ui_helptext = "Controls the Active State Power Management for PCI devices."
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" Enabling this feature can reduce power consumption of"
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" PCI-connected devices during idle times.",
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.default_value = ASPM_L0S_L1,
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.values = (const struct sm_enum_value[]) {
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{ "Disabled", ASPM_DISABLE },
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{ "L0s", ASPM_L0S },
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{ "L1", ASPM_L1 },
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{ "L0sL1", ASPM_L0S_L1 },
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SM_ENUM_VALUE_END },
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});
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static const struct sm_object pciexp_clk_pm = SM_DECLARE_BOOL({
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.opt_name = "pciexp_clk_pm",
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.ui_name = "PCI Clock Power Management",
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.ui_helptext = "Enables or disables power management for the PCI clock. When"
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" enabled, it reduces power consumption during idle states."
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" This can help lower overall energy use but may impact"
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" performance in power-sensitive tasks.",
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.default_value = true,
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});
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static const struct sm_object pciexp_l1ss = SM_DECLARE_ENUM({
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.opt_name = "pciexp_l1ss",
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.ui_name = "PCI L1 Substates",
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.ui_helptext = "Controls deeper power-saving states for PCI devices."
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" Enabling this feature allows supported devices to achieve"
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" lower power states at the cost of slightly increased"
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" latency when exiting these states.",
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.default_value = L1_SS_L1_2,
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.values = (const struct sm_enum_value[]) {
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{ "Disabled", L1_SS_DISABLED },
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{ "L1.1", L1_SS_L1_1 },
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{ "L1.2", L1_SS_L1_2 },
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SM_ENUM_VALUE_END },
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});
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#endif
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static const struct sm_object reboot_counter = SM_DECLARE_NUMBER({
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.opt_name = "reboot_counter",
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.ui_name = "Reboot Counter",
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.flags = CFR_OPTFLAG_SUPPRESS,
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.default_value = 0,
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});
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static const struct sm_object vtd = SM_DECLARE_BOOL({
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.opt_name = "vtd",
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.ui_name = "VT-d",
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.ui_helptext = "Enable or disable Intel VT-d (virtualization)",
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.default_value = true,
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});
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static struct sm_obj_form performance = {
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.ui_name = "Performance",
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.obj_list = (const struct sm_object *[]) {
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&power_profile,
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NULL
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},
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};
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static struct sm_obj_form processor = {
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.ui_name = "Processor",
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.obj_list = (const struct sm_object *[]) {
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&me_state,
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&me_state_counter,
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&vtd,
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NULL
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},
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};
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static struct sm_obj_form power = {
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.ui_name = "Power",
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.obj_list = (const struct sm_object *[]) {
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&power_on_after_fail,
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NULL
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},
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};
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static struct sm_obj_form devices = {
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.ui_name = "Devices",
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.obj_list = (const struct sm_object *[]) {
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#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE)
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&gna,
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#endif
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NULL
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},
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};
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static struct sm_obj_form pci = {
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.ui_name = "PCI",
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.obj_list = (const struct sm_object *[]) {
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#if CONFIG(SOC_INTEL_ALDERLAKE)
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&pciexp_clk_pm,
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&pciexp_aspm,
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&pciexp_l1ss,
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#endif
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NULL
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},
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};
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static struct sm_obj_form coreboot = {
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.ui_name = "coreboot",
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.obj_list = (const struct sm_object *[]) {
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&boot_option,
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&debug_level,
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&reboot_counter,
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NULL
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},
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};
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static struct sm_obj_form *sm_root[] = {
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&performance,
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&processor,
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&power,
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&devices,
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&pci,
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&coreboot,
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NULL
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};
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void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
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{
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cfr_write_setup_menu(cfr_root, sm_root);
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}
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@ -1,14 +0,0 @@
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## SPDX-License-Identifier: GPL-2.0-only
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# hardcoded
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boot_option=Fallback
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# console
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debug_level=Debug
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# cpu
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vtd=Enable
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power_profile=Balanced
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me_state=Disable
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# Devices
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wireless=Enable
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webcam=Enable
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gna=Disable
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@ -12,22 +12,10 @@ entries
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304 80 h 0 ramtop
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 2 boot_option
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388 4 h 0 reboot_counter
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# -----------------------------------------------------------------
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# coreboot config options: console
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395 4 e 3 debug_level
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# coreboot config options: cpu
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#400 8 r 0 reserved for century byte
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408 1 e 1 vtd
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416 2 e 5 power_profile
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424 1 e 4 me_state
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432 4 h 0 me_state_counter
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# coreboot config options: Devices
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504 1 e 1 wireless
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512 1 e 1 gna
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# coreboot config options: check sums
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984 16 h 0 check_sum
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@ -42,26 +30,6 @@ enumerations
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1 0 Disable
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1 1 Enable
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2 0 Fallback
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2 1 Normal
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3 0 Emergency
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3 1 Alert
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3 2 Critical
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3 3 Error
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3 4 Warning
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3 5 Notice
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3 6 Info
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3 7 Debug
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3 8 Spew
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4 0 Enable
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4 1 Disable
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5 0 Power Saver
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5 1 Balanced
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5 2 Performance
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# -----------------------------------------------------------------
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checksums
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