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mb/google/nissa/var/dirks: Add GPIO table

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Refer to the reference board of nivviks, and update GPIO settings
based on latest schematic (0W4_TWL_A_MB_0113.pdf).

BUG=b:388117663
TEST=none.

Change-Id: I5e3bc60a1c749b65c542a74eb6167e921ef369f2
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85975
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
This commit is contained in:
Ivy Jian 2025-01-14 17:18:50 +08:00 • committed by Subrata Banik
commit fe91b0c83a
2 changed files with 171 additions and 0 deletions
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6
src/mainboard/google/brya/variants/dirks/Makefile.mk Normal file
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# SPDX-License-Identifier: GPL-2.0-only
bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-y += gpio.c

165
src/mainboard/google/brya/variants/dirks/gpio.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <soc/gpio.h>
/* Pad configuration in ramstage for dirks */
static const struct pad_config override_gpio_table[] = {
/* A11 : EN_SPK_PA ==> NC */
PAD_NC(GPP_A11, NONE),
/* A14 : USB_OC1# ==> USB_A1_OC_ODL */
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
/* A15 : USB_OC2# ==> USB_A2_OC_ODL */
PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
/* A16 : USB_OC3# ==> USB_A3_OC_ODL */
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
/* A18 : NC ==> HDMI1_HPD_SUB_ODL*/
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
/* B4 : LAN_PERST_L */
PAD_CFG_GPO(GPP_B4, 1, PLTRST),
/* B14 : SPKR ==> PWM_PP3300_BUZZER */
PAD_CFG_GPO_LOCK(GPP_B14, 0, LOCK_CONFIG),
/* B16 : I2C5_SDA ==> NC */
PAD_NC(GPP_B16, NONE),
/* B17 : I2C5_SCL ==> NC */
PAD_NC(GPP_B17, NONE),
/* C0 : SMBCLK ==> NC */
PAD_NC(GPP_C0, NONE),
/* C1 : SMBDATA ==> NC */
PAD_NC(GPP_C1, NONE),
/* C3 : SML0CLK ==> NC */
PAD_NC(GPP_C3, NONE),
/* C6 : SML1CLK ==> NC */
PAD_NC(GPP_C6, NONE),
/* C7 : SML1DATA ==> NC */
PAD_NC(GPP_C7, NONE),
/* D3 : ISH_GP3 ==> NC */
PAD_NC(GPP_D3, NONE),
/* D6 : SRCCLKREQ1# ==> NC */
PAD_NC(GPP_D6, NONE),
/* D15 : ISH_UART0_RTS# ==> NC */
PAD_NC(GPP_D15, NONE),
/* D16 : ISH_UART0_CTS# ==> NC */
PAD_NC(GPP_D16, NONE),
/* E5 : [] ==> USB_A4_RT_RST_ODL */
PAD_CFG_GPO(GPP_E5, 1, DEEP),
/* E9 : USB_OC0# ==> USB_A0_OC_ODL */
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
/* E22 : DDPA_CTRLCLK ==> DDPA_CTRLCLK */
PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1),
/* E23 : DDPA_CTRLDATA ==> DDPA_CTRLDATA */
PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
/* F13 : GSXSLOAD ==> NC */
PAD_NC(GPP_F13, NONE),
/* F14 : GSXDIN ==> LAN_WAKE_ODL */
PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, DEEP, EDGE_SINGLE),
/* F15 : GSXSRESET# ==> NC */
PAD_NC(GPP_F15, NONE),
/* H6 : I2C1_SDA ==> NC */
PAD_NC(GPP_H6, NONE),
/* H7 : I2C1_SCL ==> NC */
PAD_NC(GPP_H7, NONE),
/* H8 : CNV_MFUART2_RXD ==> NC */
PAD_NC(GPP_H8, NONE),
/* H9 : CNV_MFUART2_TXD ==> NC */
PAD_NC(GPP_H9, NONE),
/* H12 : UART0_RTS# ==> NC */
PAD_NC(GPP_H12, NONE),
/* H13 : UART0_CTS# ==> NC */
PAD_NC(GPP_H13, NONE),
/* H15 : HDMI_SRC_DDC_SCL */
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
/* H17 : HDMI_SRC_DDC_SDA */
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
/* H21 : IMGCLKOUT2==> LAN_PE_ISOLATE_ODL */
PAD_CFG_GPO(GPP_H21, 1, DEEP),
/* H22 : IMGCLKOUT3 ==> NC */
PAD_NC(GPP_H22, NONE),
/* R4 : DMIC_CLK_A_0A ==> NC */
PAD_NC(GPP_R4, NONE),
/* R5 : DMIC_DATA_0A ==> NC */
PAD_NC(GPP_R5, NONE),
/* R6 : DMIC_CLK_A_1A ==> NC */
PAD_NC(GPP_R6, NONE),
/* R7 : DMIC_DATA_1A ==> NC */
PAD_NC(GPP_R7, NONE),
/* S0 : I2S1_SCLK ==> NC */
PAD_NC(GPP_S0, NONE),
/* S1 : I2S1_SFRM ==> NC */
PAD_NC(GPP_S1, NONE),
/* S2 : I2S1_TXD ==> NC */
PAD_NC(GPP_S2, NONE),
/* Configure the virtual CNVi Bluetooth I2S GPIO pads */
/* BT_I2S_BCLK */
PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
/* BT_I2S_SYNC */
PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),
/* BT_I2S_SDO */
PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),
/* BT_I2S_SDI */
PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),
/* SSP2_SCLK */
PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),
/* SSP2_SFRM */
PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),
/* SSP_TXD */
PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),
/* SSP_RXD */
PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),
};
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* GPP_B4 : [] ==> LAN_PERST_L */
PAD_CFG_GPO(GPP_B4, 0, DEEP),
/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
PAD_CFG_GPO(GPP_H20, 0, DEEP),
/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
/* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
/* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
};
static const struct pad_config romstage_gpio_table[] = {
/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
PAD_CFG_GPO(GPP_H20, 1, DEEP),
};
const struct pad_config *variant_gpio_override_table(size_t *num)
{
*num = ARRAY_SIZE(override_gpio_table);
return override_gpio_table;
}
const struct pad_config *variant_early_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}
const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(romstage_gpio_table);
return romstage_gpio_table;
}