tree: Use boolean for usb_phy_custom

Change-Id: I96decb66d632be874e517ffe1c842cd6124529b1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/mainboard/amd/birman/devicetree_glinda.cb

@@ -41,7 +41,7 @@ chip soc/amd/glinda
 
 	register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works
 
-	register "usb_phy_custom" = "1"
+	register "usb_phy_custom" = "true"
 	register "usb_phy" = "{
 		.Usb2PhyPort[0] = {
 			.compdistune = 0x3,

src/mainboard/amd/birman/devicetree_phoenix_fsp.cb

@@ -41,7 +41,7 @@ chip soc/amd/phoenix
 
 	register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works
 
-	register "usb_phy_custom" = "1"
+	register "usb_phy_custom" = "true"
 	register "usb_phy" = "{
 		.Usb2PhyPort[0] = {
 			.compdistune = 0x1,

src/mainboard/amd/birman/devicetree_phoenix_opensil.cb

@@ -41,7 +41,7 @@ chip soc/amd/phoenix
 
 	register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works
 
-	register "usb_phy_custom" = "1"
+	register "usb_phy_custom" = "true"
 	register "usb_phy" = "{
 		.Usb2PhyPort[0] = {
 			.compdistune = 0x1,

src/mainboard/amd/birman_plus/devicetree_glinda.cb

@@ -41,7 +41,7 @@ chip soc/amd/glinda
 
 	register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works
 
-	register "usb_phy_custom" = "1"
+	register "usb_phy_custom" = "true"
 	register "usb_phy" = "{
 		.Usb2PhyPort[0] = {
 			.compdistune = 0x1,

src/mainboard/amd/birman_plus/devicetree_phoenix.cb

@@ -41,7 +41,7 @@ chip soc/amd/phoenix
 
 	register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works
 
-	register "usb_phy_custom" = "1"
+	register "usb_phy_custom" = "true"
 	register "usb_phy" = "{
 		.Usb2PhyPort[0] = {
 			.compdistune = 0x1,

src/mainboard/amd/chausie/devicetree.cb

@@ -39,7 +39,7 @@ chip soc/amd/mendocino
 
 	register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works
 
-	register "usb_phy_custom" = "1"
+	register "usb_phy_custom" = "true"
 	register "usb_phy" = "{
 		.Usb2PhyPort[0] = {
 			.compdistune = 0x3,

src/mainboard/amd/mayan/devicetree_phoenix.cb

@@ -41,7 +41,7 @@ chip soc/amd/phoenix
 
 	register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works
 
-	register "usb_phy_custom" = "1"
+	register "usb_phy_custom" = "true"
 	register "usb_phy" = "{
 		.Usb2PhyPort[0] = {
 			.compdistune = 0x3,

src/mainboard/google/guybrush/variants/baseboard/devicetree.cb

@@ -98,7 +98,7 @@ chip soc/amd/cezanne
 
 	register "pspp_policy" = "DXIO_PSPP_BALANCED"
 
-	register "usb_phy_custom" = "1"
+	register "usb_phy_custom" = "true"
 	register "usb_phy" = "{
 		/* Left USB C0 Port */
 		.Usb2PhyPort[0] = {

src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb

@@ -28,7 +28,7 @@ end
 
 chip soc/amd/cezanne
 
-	register "usb_phy_custom" = "1"
+	register "usb_phy_custom" = "true"
 	register "usb_phy" = "{
 		/* Left USB C0 Port */
 		.Usb2PhyPort[0] = {

src/mainboard/google/myst/variants/baseboard/devicetree.cb

@@ -85,7 +85,7 @@ chip soc/amd/phoenix
 	register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO(b/277214353): reenable when PSPP works
 	register "s0ix_enable" = "true"
 
-	register "usb_phy_custom" = "1"
+	register "usb_phy_custom" = "true"
 	register "usb_phy" = "{
 		.Usb2PhyPort[0] = {
 			.compdistune = 0x3,

src/soc/amd/cezanne/chip.h

@@ -93,7 +93,7 @@ struct soc_amd_cezanne_config {
 		DXIO_PSPP_POWERSAVE,
 	} pspp_policy;
 
-	uint8_t usb_phy_custom;
+	bool usb_phy_custom;
 	struct usb_phy_config usb_phy;
 
 	/* eDP phy tuning settings */

src/soc/amd/glinda/chip.h

@@ -103,7 +103,7 @@ struct soc_amd_glinda_config {
 		DXIO_PSPP_POWERSAVE,
 	} pspp_policy;
 
-	uint8_t usb_phy_custom;
+	bool usb_phy_custom;
 	struct usb_phy_config usb_phy;
 };
 

src/soc/amd/mendocino/chip.h

@@ -168,7 +168,7 @@ struct soc_amd_mendocino_config {
 		DXIO_PSPP_POWERSAVE,
 	} pspp_policy;
 
-	uint8_t usb_phy_custom;
+	bool usb_phy_custom;
 	struct usb_phy_config usb_phy;
 	/* Set for PCIe optimization w/a and a double confirming on the result of PCIe Signal
 	   Integrity is highly recommended. */

src/soc/amd/phoenix/chip.h

@@ -107,7 +107,7 @@ struct soc_amd_phoenix_config {
 		DXIO_PSPP_POWERSAVE,
 	} pspp_policy;
 
-	uint8_t usb_phy_custom;
+	bool usb_phy_custom;
 	struct usb_phy_config usb_phy;
 
 #if !CONFIG(PLATFORM_USES_FSP2_0)