Update the SaGV frequency registers
- (`sagv_freq_mhz[1]`) in the devicetree from "3200" to "4800".
- (`sagv_freq_mhz[2]`) in the devicetree from "6000" to "6400".
- (`sagv_freq_mhz[3]`) in the devicetree from "6400" to "6800".
This change likely to improve the device performance.
BUG=b:328770565, b:407862619
TEST=Able to reduce the boot time by 18ms.
Change-Id: Id0b25adeed4b3f3e1c37d17901006a2db2d21223
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87087
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Correct XHCI and PHY register addresses and enable USB port 3 VBUS
to support USB host functionality.
BUG=b:379008996
BRANCH=none
TEST=build pass
Signed-off-by: Liu Liu <ot_liu.liu@mediatek.corp-partner.google.com>
Change-Id: I5f1b4b3eb178cb9a110b97a2763c8cff5cdf0ddd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87021
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Initialize SPI NOR Flash Controller (SNFC) in the bootblock to
enable CBFS and execute other stages such as verstage, romstage,
ramstage, etc.
BUG=b:379008996
BRANCH=none
TEST=Read NOR flash data successfully.
Signed-off-by: Noah Shen <noah.shen@mediatek.corp-partner.google.com>
Change-Id: Icf4af32dd9d8c704fd7246adda94dfa3350bb672
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This board does not have a DMIC, so don't try to disable.
Change-Id: Ic47f9c3b40dd76a78325b024ba8f93a117f7d031
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87095
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: Icfb80295ba0c55184b174a63756e8779111d9b76
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87122
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPP_F10 is not connected, so configure it accordingly.
Change-Id: I5a8fb34837b1b3f2f066ccc260f0ab749d7782c0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87121
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These are not connected to anything, so configure them accordingly.
Change-Id: Ia3a528faf74c23d0b78210b22c6e8d3f69de8184
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This GPIO is only used for full PCI wireless, and these boards use
CNVi so disconnect it.
Change-Id: Ie7be00543b5c99814204265157eeab654492724f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87119
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure all strap GPIOs as outputs, rather than some being not
connected. This doesn't change anything, but is more explicit.
Set these all to sample on RSMRST.
Change-Id: I0b0eb72c68d2fbe7920db798c2a625d7cc7e8063
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: Id0f00b9b4be06da1d58cfb4491eb7606cc968459
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87116
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: If1c102ecf9982dce1bd79175266451ed80da09f3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87115
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: Ia8a2ff8f370fef6249b1edbb08e00a01dedc3a07
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87113
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: Ibd60b124efa4f5cb0688ee097574884b9912fb66
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87112
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: I8dd5fade69b9e1c2b24b8ffaeac7f72e72894b9c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87111
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: I5ba2e400ec57a0c52523ea360bee17d9517454b5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87110
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: Ib86d4b0193fc78123ab3451e92865bff2bab5bd6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87106
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable `VBOOT_EARLY_EC_SYNC` for rull device. This enables EC software
sync in romstage. This is useful to achieve full USB-PD negotiation
early in the boot flow. It eliminates a problem seen in rull devices
where PMC is wrongly configured in depthcharge during the EC-sync
scenario which prevents USB devices from getting detected when
connected via a self-powered USB hub.
BUG=b:386920751
TEST=Verify detection and booting to OS from USB drive connected to the
Servo v4 debugger (self-powered hub) during the EC-sync scenario.
Change-Id: Ie36794a8a2c0bcd4ba77f3ad844a30f28f59403f
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
The parent project kuldax had support wifi sar switch.
But moxie does not support Wifi sar. Remove wifi sar table.
BUG=b:248367859
TEST=build pass
Change-Id: I012ff2d9c8c4d6d4480cae7166bf8e633bcaa752
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Dirks is chromebox, enable early graphics support for HDMI.
BUG=b:399236160
TEST=On-screen text message seen during MRC training on dirks
Change-Id: I8ab2c3a2cc72059facbbc0bba59cc480a5081a9e
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit modifies the handling of PCH High Definition Audio (HDA)
Serial Digital Interface (SDI) enablement.
- In `devicetree.cb`, the static `pch_hda_sdi_enable` property is
removed to allow varaints to override if needed.
- In `variant.c`, `variant_update_soc_memory_init_params` is
introduced to dynamically configure `PchHdaSdiEnable` UPD based on
the firmware configuration (for example: `AUDIO_ALC256_HDA` or
`AUDIO_ALC256M_CG_HDA`).
SDI is enabled if this FW config option is present. Otherwise, it
defaults to disabled.
- `variant.c` is now added for romstage as well because the SDI
configuration needs to happen earlier in the boot process.
BUG=b:328770565, b:407876136
TEST=Able to reduce the boot time by 18ms for SKUs w/o HDA audio.
Change-Id: Ice28ea7445a5cb32fe8263ada363d4f45c3152f5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87090
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit introduces a mechanism to allow mainboards to override
the default FSP-M UPDs for Panther Lake.
- Adds `variant_update_soc_memory_init_params` as a weak function
in `variants.h` and `romstage.c` for board-specific implementations.
- In `romstage.c`, `mainboard_memory_init_params` now calls
`variant_update_soc_memory_init_params` to apply board-specific
overrides to the FSP-M UPDs.
This enables finer-grained control over memory initialization parameters
at the variant level.
BUG=b:328770565
TEST=Able to build and boot google/fatcat.
Change-Id: I403bc4270ef526363defa6cd7d22741ad42a8a76
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87089
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These are the final notes for the release.
Change-Id: I5daaae609b9271c543009c303db948fa7aa24b6d
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87134
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: I5643fe19f349facffab218e0e8da02d88f192e73
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: Ifd24ca28d66e5e987129a44b6682efab9b64049b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87103
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: I9563f1d3f464b3be35d18d6cd6fbbcee314fce28
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87102
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a non-functional change, and only makes the GPIOs easier to
read.
Change-Id: Id6a30adbc434c975cda1cdcffd164650910e1da3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: Ic5c541a44ac9b34dad5430c994b1fa28e96d67f4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87100
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: I5e271508fcd99c01f7de4e5dad7a1941ba1968ec
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These aren't required, so remove the config and let FSP handle it.
Change-Id: I143a779950773823746e838cf29209b6e3bb87ad
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87097
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set GPP_F2 to output high, to indicate that CNVi is disabled.
Change-Id: I82f3ce699d5e823e1ce942acb7a0ba1bd548d9a0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Configure all strap GPIOs as outputs, rather than some being not
connected. This doesn't change anything, but is more explicit.
Set these all to sample on RSMRST.
Change-Id: I779b6bc486b68e8df50347540364901507a7102c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This is a non-functional change; it just makes it easier to read.
Change-Id: Ib3f87c6e3e83d57c4e6969c3aac7cae02d750a5c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This GPIO is not connected so configure it accordingly.
Change-Id: Ie85d69e0a2a423261038688c176b32abe7bd8134
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: I658cd6ddf2d418da0e36a8e1969041a696a10d87
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.
Enable and reset GPIOs are configured as per pin mapping in gpio.c.
BUG=b:391612392
TEST=Run suspend_stress_test on gimble device and verify that the
device suspends to S0ix.
Change-Id: Iac9eb63639cbb0c7708d5b2bb30aca20e09db3e7
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.
Enable and reset GPIOs are configured as per pin mapping in gpio.c.
BUG=b:391612392
TEST=Run suspend_stress_test on redrix device and verify that the
device suspends to S0ix.
Change-Id: I9d8bd6bb2c5aecf2fa67486cc81935d2ac7cd5ce
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87058
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.
Enable and reset GPIOs are configured as per pin mapping in gpio.c.
BUG=b:391612392
TEST=Run suspend_stress_test on mithrax device and verify that the
device suspends to S0ix.
Change-Id: I5008ec5e153c3695b1d6aa1183515eba192deaa2
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87060
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.
Enable and reset GPIOs are configured as per pin mapping in gpio.c.
BUG=b:391612392
TEST=Run suspend_stress_test on anahera device and verify that the
device suspends to S0ix.
Change-Id: I43a1277efabf8b1ca265e9aca65878da60275b38
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87057
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
This reverts commit 08076240bd.
Reason for revert: Unable to boot to OS on taniks. Enabling RTD3 for
pcie_rp9 in the brya baseboard enables it for all variants. pcie_rp9
is being used for eMMC in taniks, taeko and few other variants. This
is causing boot failure in these devices.
Change-Id: I72270812312db5b2505046f32466cbb4c200947f
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87056
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When CONFIG_PCI is disabled, but COMMONLIB_STORAGE and
COMMONLIB_STORAGE_SD are enabled, the compilation of
pci_sdhci.c fails. This is because the code attempts to use
pci_s_read_config32() with the PCI_BASE_ADDRESS_0 macro, which
are only defined when CONFIG_PCI is enabled.
Add an early return NULL check based on !CONFIG(PCI) at the
beginning of new_pci_sdhci_controller(). This prevents the
compiler from attempting to process the PCI-specific code path
when PCI support is not configured, resolving the build failure
in this specific Kconfig scenario.
TEST=Able to build herobrine.
Change-Id: I5c70d9b9ebcac13b47bba2c260fdf2ad7d56d4d7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The double negation (`!!`) was unnecessarily used when assigning the
`pch_hda_sdi_enable` type boolean from the SOC config to the FSP M
config.
This commit removes the redundant `!!` operator, directly assigning
the boolean value of `config->pch_hda_sdi_enable[i]` to
`m_cfg->PchHdaSdiEnable[i]`.
TEST=Able to build and boot google/fatcat.
Change-Id: I9233116ca2bfaeac2f685d464a1cb261f067db6a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87109
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
The barrel charger check in `baseboard_devtree_update` was
unconditional, increasing boot time on platforms without it.
This commit conditions the check on `CONFIG(BOARD_GOOGLE_MODEL_FATCAT)`,
making it specific to the fatcat board.
This avoids unnecessary delay on platforms like francka and felino.
BUG=b:328770565
TEST=Boot time reduced by 56ms.
Change-Id: Id7a26b634a1a310f714fbf4b4a2accd75665bc28
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87064
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
The arch include files are overshadowed by PSP verstage include files.
The reason is that psp_verstage implements its own set of inb() and
outb() functions, which use a runtime configurable IO base address
instead of a built time constant.
But this works at the moment only because of the order in which the
include files are added. Since that is very error prone, this patch
introduces another solution to the problem.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I16fa4a4cb5168024aaef30119e9aa8a34dbaacbe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
