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mb/google/brya/var/anahera: Enable RTD3 for SSD to resolve S0ix issue

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Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.

Enable and reset GPIOs are configured as per pin mapping in gpio.c.

BUG=b:391612392
TEST=Run suspend_stress_test on anahera device and verify that the
device suspends to S0ix.

Change-Id: I43a1277efabf8b1ca265e9aca65878da60275b38
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87057
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
This commit is contained in:
Pranava Y N 2025-04-01 16:24:27 +05:30 • committed by Subrata Banik
commit 8b55ee05dc
1 changed files with 9 additions and 0 deletions
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9
src/mainboard/google/brya/variants/anahera/overridetree.cb
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@ -227,6 +227,15 @@ chip soc/intel/alderlake
device generic 0 on end
end
end #PCIE8 SD card
device ref pcie_rp9 on
chip soc/intel/common/block/pcie/rtd3
register "is_storage" = "true"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
register "srcclk_pin" = "1"
device generic 0 on end
end
end #PCIE9-12 SSD
device ref i2c0 on
chip drivers/i2c/generic
register "hid" = ""10EC5682""