Add H58G56DK9BX068 in the memory_parts.json and re-generate the SPD.
BUG=none
TEST= Booted successfully on nvlrvp board using H58G56DK9BX068.
util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: I7f8e13c2dac50b108f3ded1528a48b641eafbeec
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90856
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This aligns with the corrected indexing scheme used in the SoC VR
configuration code.
Ref=:830097_WCL_PDG_SchChk_Rev1p5
BUG=b:None
TEST=Build ocelot and verify that the system boots
Change-Id: I948c9233f4a5518992891b90fb9bb6a3793baa5f
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Set IA voltage regulator to use IRMS mode with 28 second time window
for more accurate thermal design current measurement.
Ref=:830097_WCL_PDG_SchChk_Rev1p5
BUG=b:None
TEST=Build ocelot and verify that the system boots with the following
VR parameter
[SPEW ] TdcMode[0]:0x1
[SPEW ] TdcMode[1]:0x0
[SPEW ] TdcMode[2]:0x0
[SPEW ] TdcMode[3]:0x0
[SPEW ] TdcTimeWindow[0]:0x6D60
[SPEW ] TdcTimeWindow[1]:0x0
[SPEW ] TdcTimeWindow[2]:0x0
[SPEW ] TdcTimeWindow[3]:0x0
Change-Id: I4b7b9484d47cf9d98548cfc8b53e47be4e21c4d1
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91455
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When ramstage is not LZ4 compressed then don't include the LZ4
decompressor into postcar stage.
TEST=Reduces postcar size on Lenovo x220 by 1224 bytes.
Change-Id: I51e25d94213b42474c8cedd9e7bae9e81568566d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91385
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This board no longer uses option table, so the config is invalid.
Change-Id: I62268472e9a2020e81c352933aa9bac8bb2fcddd
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91541
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The LCD MIPI panel requires proper power-off commands before reset.
Skipping them may cause overpotential conditions, leading to image
stickiness or flicker.
On MTK platforms, CR50 reset is the only reboot path in coreboot.
Add mainboard_prepare_cr50_reset() implementation on skywalker to
power off the MIPI panel before issuing CR50 reset.
BUG=b:474187570
TEST=emerge-jedi coreboot chromeos-bootimage
BRANCH=skywalker
Change-Id: I46a654e03ca2e7374cdaf05729f12b182669a64f
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91507
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Zhengqiao Xia <xiazhengqiao@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce mtk_mipi_panel_poweroff() in common display layer and
mtk_dsi_panel_poweroff() in DSI driver. The DSI mode flags are
saved during init and reused for the power-off command path.
BUG=b:474187570
TEST=emerge-jedi coreboot chromeos-bootimage
BRANCH=skywalker
Change-Id: Ic684822bc5f20d3e2f5ce3d44035c902a2b44184
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91432
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhengqiao Xia <xiazhengqiao@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The commit 7072f42c08f7 ("soc/mediatek/mt8196: Move WATCHDOG_TOMBSTONE
from SRAM to SRAM_L2C") move WATCHDOG_TOMBSTONE from SRAM to SRAM_L2C
causes elog_handle_watchdog_tombstone (BS_POST_DEVICE, BS_ON_ENTRY) to
be invoked after mtk_mmu_disable_l2c_sram. As a result, the watchdog
event magic value in WATCHDOG_TOMBSTONE is cleared before it can be
processed, which is incorrect behavior.
So we refactor the mtk_mmu_disable_l2c_sram to be called as a boot state
entry (BS_POST_DEVICE, BS_ON_EXIT) instead of directly from soc_init.
This ensures that mtk_mmu_disable_l2c_sram will be executed after
elog_handle_watchdog_tombstone.
BUG=b:481854714
TEST=watchdog event added to eventlog on WDT timeout (triggered via echo > /dev/watchdog)
TEST=cbmem logs preserved on WDT timeout
Change-Id: I69ef567ab73f2f7006bb249cb577f377d4720909
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The purpose of the WATCHDOG_TOMBSTONE section is to temporarily record
the watchdog timeout event, before triggering the reboot. Then, in the
next boot, if WATCHDOG_TOMBSTONE contains the watchdog event magic, then
a watchdog event will be added to the event log.
The flow relies on the fact that the WATCHDOG_TOMBSTONE section can be
preserved across AP resets. However, for MT8196, the whole SRAM region
will be powered down during AP reset via GPIO AP_SYSRST_ODL (SYSRSTB).
On MT8196, L3C (used as SRAM_L2C) is powered on by default. Also, per
MT8196 PMIC configuration, a SYSRSTB reset will retain the L3C power.
Therefore, region data in SRAM_L2C can be preserved across AP resets.
Fix the WATCHDOG_TOMBSTONE preservation by moving it to SRAM_L2C.
Reduce PRERAM_CBMEM_CONSOLE by 1K for WATCHDOG_TOMBSTONE.
BUG=b:481854714
TEST=watchdog event added to eventlog on WDT timeout:
17 | 2026-03-04 08:57:17+0000 | Hardware watchdog reset
TEST=cbmem logs preserved on WDT timeout
Change-Id: I630d1749e1a743069f2d814efe0a4994889a2a3f
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91540
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Communication with GSC and EC is abnormal because Mica is
missing the following configurations: DRIVER_TPM_I2C_BUS,
EC_GOOGLE_CHROMEEC_SPI_BUS,and MAINBOARD_GPIO_PIN_FOR_GSC_AP_INTERRUPT.
BUG=b:489062509,b:489264026
TEST=build mica board, flash to Quenbi to verify the GSC and
EC communication functionality.
Check if there are any further abnormalities in the bootup log:
For GSC:
Probing TPM I2C: Cr50 TPM IRQ timeout!
For EC:
crosec_spi_io: Timeout waiting for framing byte.
Change-Id: I2ff158968f946eb780d593c8b1d1e8b07f95ce8a
Signed-off-by: KangMin Wang <kangmin.wang@luxshare.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91517
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Replace platform-specific finalize.c with the common finalize
implementation.
Changes:
- Remove src/soc/intel/pantherlake/finalize.c
- Enable SOC_INTEL_COMMON_FEATURE_FINALIZE in Kconfig
- Update Makefile.mk to remove finalize.c from build
The finalize implementation was identical to Meteor Lake, making
it an ideal candidate for consolidation.
Change-Id: I749eea246fdc7ab89848ed4160c61666e8944095
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Replace platform-specific finalize.c with the common finalize
implementation.
Changes:
- Remove src/soc/intel/meteorlake/finalize.c
- Enable SOC_INTEL_COMMON_FEATURE_FINALIZE in Kconfig
- Update Makefile.mk to remove finalize.c from build
The finalize implementation was identical to Panther Lake, making
it an ideal candidate for consolidation.
Change-Id: Id0c3bde3b721b7a3e497711cfc6dd21efbfda4c5
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
This introduces a common finalize implementation for Intel SoCs that
consolidates the nearly identical finalize.c files across Meteor Lake
and Panther Lake platforms.
The implementation includes:
- pch_finalize(): TCO lockdown and PMC status clearing
- tbt_finalize(): Disable Thunderbolt PCIe root ports bus master
- sa_finalize(): Lock system agent PAM regions when coreboot handles
chipset lockdown
- heci_finalize(): Set HECI to D0i3 and optionally disable HECI1
- soc_finalize(): Main finalization sequence coordinating all the above
This consolidation eliminates duplicate code and ensures consistent
finalization behavior across platforms. Alder Lake is intentionally
excluded as it has additional platform-specific camera clock (ISCLK)
configuration that would complicate the common implementation.
The common driver is enabled via the SOC_INTEL_COMMON_FEATURE_FINALIZE
Kconfig option.
Platforms that will use this common implementation:
- Meteor Lake
- Panther Lake
Change-Id: I4dd9ccf7e14fecdded92da6bf366e6ff56d866a4
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91227
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace platform-specific reset.c with the common global reset
implementation using CSE with PMC fallback.
Changes:
- Remove src/soc/intel/elkhartlake/reset.c
- Enable SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC in Kconfig
- Update Makefile.mk to remove reset.c from build
The global reset implementation was identical to 6 other platforms,
making it an ideal candidate for consolidation.
Change-Id: I635347f15e35ec8e69c24edcec8c45c55a496ffd
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Replace platform-specific reset.c with the common global reset
implementation using CSE with PMC fallback.
Changes:
- Remove src/soc/intel/jasperlake/reset.c
- Enable SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC in Kconfig
- Update Makefile.mk to remove reset.c from build
The global reset implementation was identical to 6 other platforms,
making it an ideal candidate for consolidation.
Change-Id: Ia039b25b21b4af5912dd5e8af9ef06a66c00a7bd
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Replace platform-specific reset.c with the common global reset
implementation using CSE with PMC fallback.
Changes:
- Remove src/soc/intel/cannonlake/reset.c
- Enable SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC in Kconfig
- Update Makefile.mk to remove reset.c from build
The global reset implementation was identical to 6 other platforms,
making it an ideal candidate for consolidation.
Change-Id: If5a70a0e05c50ab893ba8861e200b078982dfad9
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91213
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace platform-specific reset.c with the common global reset
implementation using CSE with PMC fallback.
Changes:
- Remove src/soc/intel/tigerlake/reset.c
- Enable SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC in Kconfig
- Update Makefile.mk to remove reset.c from build
The global reset implementation was identical to 6 other platforms,
making it an ideal candidate for consolidation.
Change-Id: I1bf9d4eeab0fecbb33d122a32ecdeef85af059fa
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Replace platform-specific reset.c with the common global reset
implementation using CSE with PMC fallback.
Changes:
- Remove src/soc/intel/pantherlake/reset.c
- Enable SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC in Kconfig
- Update Makefile.mk to remove reset.c from build
The global reset implementation was identical to 6 other platforms,
making it an ideal candidate for consolidation.
Change-Id: I9bd0dae5bbfc0ec2e9101e848de2037760314456
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Replace platform-specific reset.c with the common global reset
implementation using CSE with PMC fallback.
Changes:
- Remove src/soc/intel/meteorlake/reset.c
- Enable SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC in Kconfig
- Update Makefile.mk to remove reset.c from build
The global reset implementation was identical to 6 other platforms,
making it an ideal candidate for consolidation.
Change-Id: I0ad75bbeb1fad7352b2b898487a5b54eff496d0b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Replace platform-specific reset.c with the common global reset
implementation using CSE with PMC fallback.
Changes:
- Remove src/soc/intel/alderlake/reset.c
- Enable SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC in Kconfig
- Update Makefile.mk to remove reset.c from build
The global reset implementation was identical to 6 other platforms,
making it an ideal candidate for consolidation.
Change-Id: Iebaf5bafd5a97dde37ffc435b2ad8b6a8dcfecd0
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
This introduces a common implementation of do_global_reset() that
uses CSE (Converged Security Engine) with PMC (Power Management
Controller) fallback. This implementation is identical across 7
Intel client platforms.
The function attempts to request a global reset from the CSE first,
which is the preferred method. If CSE is unavailable or the request
fails, it falls back to enabling PMC-based global reset and
triggering a full reset.
This consolidates the global reset handling and eliminates duplicate
code across multiple platforms. The common implementation is enabled
via the SOC_INTEL_COMMON_RESET_GLOBAL_RESET_CSE_PMC Kconfig option.
Platforms that will use this common implementation:
- Alder Lake
- Meteor Lake
- Panther Lake
- Tiger Lake
- Cannon Lake
- Jasper Lake
- Elkhart Lake
Change-Id: Ida59bc2df483db5397ee043f66fdee56508bd0df
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91208
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace platform-specific lockdown.c with the common PMC lockdown
driver.
Changes:
- Remove src/soc/intel/pantherlake/lockdown.c
- Add PMC_FDIS_LOCK_REG define pointing to GEN_PMCON_B in soc/pmc.h
- Enable SOC_INTEL_COMMON_FEATURE_PMC_LOCKDOWN in Kconfig
- Update Makefile.mk to remove lockdown.c from build
Panther Lake uses GEN_PMCON_B for ST_FDIS_LOCK (bit 21), the same
approach as Meteor Lake.
Change-Id: I9becbedbb1bcbc19f60d3ebb024dd5e43c7cee29
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91207
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace platform-specific lockdown.c with the common PMC lockdown
driver.
Changes:
- Remove src/soc/intel/meteorlake/lockdown.c
- Add PMC_FDIS_LOCK_REG define pointing to GEN_PMCON_B in soc/pmc.h
- Enable SOC_INTEL_COMMON_FEATURE_LOCKDOWN in Kconfig
- Update Makefile.mk to remove lockdown.c from build
Meteor Lake uses GEN_PMCON_B for ST_FDIS_LOCK (bit 21), the same
approach as Panther Lake.
Change-Id: Iecccc482f04d85cfec738dd57dc1473eaf82cfcc
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Replace platform-specific lockdown.c with the common PMC lockdown
driver introduced in the previous commit.
Changes:
- Remove src/soc/intel/alderlake/lockdown.c
- Add PMC_FDIS_LOCK_REG define pointing to ST_PG_FDIS1 in soc/pmc.h
- Enable SOC_INTEL_COMMON_FEATURE_PMC_LOCKDOWN in Kconfig
- Update Makefile.mk to remove lockdown.c from build
Alder Lake uses the ST_PG_FDIS1 register (0x1e20) for ST_FDIS_LOCK,
which differs from newer platforms that use GEN_PMCON_B. This
difference is handled through the PMC_FDIS_LOCK_REG define.
Change-Id: Ic80aca618dcbe5a4fef54f4802e6f4ce6f4ebd44
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91205
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Wildcat Point's GPIOs work the same as Lynx Point LP's GPIOs.
Change-Id: I64963937a5b40bcab605acb826567d63af512427
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91468
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The idea is to use Haswell's acpi.c file in the next commit, and this
little difference affects reproducibility.
Change-Id: Ib2641586fbb9e8ed175eeca0bd665057f5049c0e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Device NVS is only used in southbridge code. This change is
non-reproducible.
Change-Id: I60ce9a80d6e3e0ce0c13037d4caae473d3d092a9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91402
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Device NVS is only used in southbridge code. Also move the platform.asl
file since it is mostly about southbridge stuff.
Tested with BUILD_TIMELESS=1, Purism Librem 15 v2 remains identical.
Change-Id: Ia0d301f6b77f7084a6d1dfe1238693c76c62ef7a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91401
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since this used to be a SoC (no distinction between CPU/NB/SB parts),
all the headers were in a single place. Move headers about PCH things
to where they belong.
Change-Id: I296f57f5575d026ad87698e972eb9f448d54d09b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
In preparation to unify the Haswell and Broadwell codebases, move the
remaining Broadwell SoC code to the northbridge folder.
This change only moves the files, and does the minimal amount of edits
so that boards still build. Most of those edits boil down to "find and
replace".
Change-Id: I5bde032ee824a90328a78403ea03d39ad20f2b09
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The PCH split was done many moons ago, in order to unify two codebases
with overlapping hardware support: Haswell + Lynx Point and Broadwell.
The on-package PCH found in Broadwell ULT/ULX CPUs is Wildcat Point.
This change only moves the files, and does the minimal amount of edits
so that boards still build. Most of those edits boil down to "find and
replace".
Change-Id: I29235b47970f81b5db6717801f2ab771ff980476
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91396
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on Wildcat Point and checked against version 1.9.1 of PCH
reference code. Note that this runs later in the init sequence,
compared to Wildcat Point, as it is easier to get the values of
the STRPFUSECFG registers this way.
Change-Id: I0fadd33d043e66c10d29dcf8ba9724723ad70a9b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91467
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Taken from Wildcat Point and checked against version 1.9.1 of PCH
reference code. Note down a few TODOs to be done after Lynx Point
and Wildcat Point code has been unified.
Change-Id: I91aa3f0a5ea67bd43a625f37527c9d41c277b990
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91466
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Implementation taken from Wildcat Point (Broadwell) code. This reduces
differences between both platforms.
Change-Id: Id3b6efcbc416929245fcaf329521d49fee0b457f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Commit 4c4bd3cd97 ("soc/intel/broadwell: Hook up PCI domain and CPU
cluster ops to devicetree") and commit 600fa266bd ("nb/intel/haswell:
Hook up PCI domain and CPU cluster ops to devicetree") decoupled the CPU
bus device operations from northbridge code. Since Haswell and Broadwell
both use the same CPU code, move the CPU bus ops to CPU code in order to
deduplicate them.
Change-Id: I11cbff3d87e233f40a40f2fc70840f6bf35b0cb9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91463
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When SOC_INTEL_COMPLIANCE_TEST_MODE is enabled, disable PCIe clock
gating and power gating to prevent the controller from entering power
management states that would interfere with PCIe compliance testing.
This ensures stable operation during PCIe TX compliance tests by
keeping the PCIe controller in an active state throughout the test
process.
Affected/Verified Platforms:
- PTL: Lapis, Ruby
- WCL: Matsu, Ocicat, Kodkod
BUG=b:451560515
TEST="Run PCIe Compliance TX test successfully"
Change-Id: I92f442d24219af78310ce04b782735beed9c58e6
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90325
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I do push patches for autoport somewhat often (by autoport standards)
and have reviewed many patches for it in the past couple of years, so
add myself as a maintainer.
Change-Id: I897032eea898ff254d02df4d100e27966a6fc6ae
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Philipp Groß <jeangrande@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Remove explicit overrides for disable_c1_state_auto_demotion and
disable_package_c_state_demotion, reverting to the SoC default behavior
which allows the hardware to autonomously demote C1 and package
C-states.
BUG=b:455612673
TEST=Boot to OS on Google fatcat
Change-Id: Ica9348e668c64ac2b27f3970b23f963ba0a2e753
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Turn off Gen4 and Gen5 NVMe power at bootblock and turn on at romstage
to address device enumeration and link speed issues observed after power
cycles and warm/cold reboots. This change specifically resolves issues
seen with certain NVMe devices, particularly the Micron 3500, where
improper power sequencing can cause enumeration failures or incorrect
link speed negotiation.
BUG=none
TEST=Boot Fatcat board with Micron 3500 NVMe in Gen4/Gen5 M.2
slots. Perform multiple power cycles and warm/cold reboots. Verify
consistent NVMe enumeration and proper link speed using lspci output.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ie929a3010acd74237d29a77c7582f1cae837a2e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91369
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If `CONFIG(DEBUG_RAM_SETUP)`, dump the values of the CAPID0_A and
CAPID0_B registers to the log. This is useful debugging information.
Dump the CAPID registers' values before native chipset init, because
dynamic fusing changes the CAPID values.
Tested on ASRock Z97 Extreme6 with a PCIe card plugged into the PCIE4
slot (forcing PEG to be bifurcated as x8+x8). The CPU and PCH are:
CPU id(306c3) ucode:00000028 Intel(R) Core(TM) i7-4770S CPU @ 3.10GHz
AES supported, TXT supported, VT supported
PCH type: Z97, device id: 8cc4, rev id 0
CAPID values before dynamic fusing are shown below:
CAPID0_A: 0x6204e861
DDR3L 1.35V: Yes
DDR Write Vref: No
OC enabled (DSKU): No
DDR overclock: No
Compatibility RID: 0x6
Capability DID: Desktop
DID override: No
Integrated GPU: No
Dual channel: Yes
X2APIC support: Yes
DIMMs per channel: 1
Camarillo device: No
Full ULT info: Yes
DDR 1N mode: Yes
PCIe ratio: No
Max channel size: 16 GiB
PEG Gen2 support: Yes
DMI Gen2 support: Yes
VT-d support: Yes
ECC forced: No
ECC supported: No
DMI width: x4
Width upconfig: Yes
PEG function 0: Yes
PEG function 1: No
PEG function 2: No
Disp HD audio: Yes
CAPID0_B: 0x565400d0
PEG for GFX single: Unlimited width
PEG for GFX multi: Unlimited width
133 MHz ref clock: Up to DDR3-1600
Silicon mode: Production
HDCP capable: Yes
Num PEG lanes: 16
Add. GFX capable: Yes
Add. GFX enable: Yes
CPU Package Type: 0
PEG Gen3 support: No
100 MHz ref clock: Up to DDR3-1600
Soft Bin capable: No
Cache size: 3
SMT support: Yes
OC enabled (SSKU): No
OC controlled by: SSKU
CAPID values after dynamic fusing are shown below, with manually
added arrows to indicate which values have changed:
CAPID0_A: 0x4204a06d
DDR3L 1.35V: Yes
DDR Write Vref: No
OC enabled (DSKU): Yes <-----
DDR overclock: Yes <-----
Compatibility RID: 0x6
Capability DID: Desktop
DID override: No
Integrated GPU: Yes <-----
Dual channel: Yes
X2APIC support: Yes
DIMMs per channel: 2 <-----
Camarillo device: No
Full ULT info: Yes
DDR 1N mode: Yes
PCIe ratio: No
Max channel size: 16 GiB
PEG Gen2 support: Yes
DMI Gen2 support: Yes
VT-d support: Yes
ECC forced: No
ECC supported: No
DMI width: x4
Width upconfig: Yes
PEG function 0: Yes
PEG function 1: Yes <-----
PEG function 2: No
Disp HD audio: Yes
CAPID0_B: 0x564400d0
PEG for GFX single: Unlimited width
PEG for GFX multi: Unlimited width
133 MHz ref clock: Up to DDR3-1600
Silicon mode: Production
HDCP capable: Yes
Num PEG lanes: 16
Add. GFX capable: Yes
Add. GFX enable: Yes
CPU Package Type: 0
PEG Gen3 support: Yes <-----
100 MHz ref clock: Up to DDR3-1600
Soft Bin capable: No
Cache size: 3
SMT support: Yes
OC enabled (SSKU): No
OC controlled by: SSKU
Change-Id: I46f27c54a7ec7fd9fc79fdabaa59a44a591168b8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91478
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
