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nb/intel/broadwell/bootblock.c: Use Haswell's file

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Tested with BUILD_TIMELESS=1, Purism Librem 15 v2 remains identical.

Change-Id: Ie583224b4cfc4116e6cdb511793b8c39e8bf679e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91400
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2026-02-23 22:03:33 +01:00 • committed by Matt DeVillier
commit 3d4f2efcf7
2 changed files with 1 additions and 35 deletions
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2
src/northbridge/intel/broadwell/Makefile.mk
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@ -2,7 +2,7 @@
ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y)
bootblock-y += bootblock.c
bootblock-y += ../haswell/bootblock.c
romstage-y += early_init.c
romstage-y += raminit.c

34
src/northbridge/intel/broadwell/bootblock.c
View file

@ -1,34 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/bootblock.h>
#include <assert.h>
#include <device/pci_ops.h>
#include <soc/pci_devs.h>
#include <soc/systemagent.h>
static uint32_t encode_pciexbar_length(void)
{
switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 1 << 1;
case 64: return 2 << 1;
default: return dead_code_t(uint32_t);
}
}
void bootblock_early_northbridge_init(void)
{
/*
* The "io" variant of the config access is explicitly used to setup the
* PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to true. That way, all
* subsequent non-explicit config accesses use MCFG. This code also assumes
* that bootblock_northbridge_init() is the first thing called in the non-asm
* boot block code. The final assumption is that no assembly code is using the
* CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
*/
const uint32_t reg = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0);
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg);
}