erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

sb/intel/lynxpoint/pcie.c: Add additional disable steps

Browse source 
Taken from Wildcat Point and checked against version 1.9.1 of PCH
reference code. Note down a few TODOs to be done after Lynx Point
and Wildcat Point code has been unified.

Change-Id: I91aa3f0a5ea67bd43a625f37527c9d41c277b990
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91466
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Angel Pons 2026-02-28 00:15:31 +01:00 • committed by Matt DeVillier
commit 8b69dcccb2
1 changed files with 21 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

21
src/southbridge/intel/lynxpoint/pcie.c
View file

@ -3,6 +3,7 @@
#include <assert.h>
#include <commonlib/helpers.h>
#include <console/console.h>
#include <delay.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pciexp.h>
@ -326,6 +327,26 @@ static void root_port_commit_config(void)
pci_and_config16(dev, PCI_COMMAND,
~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
/* 8.2 Configuration of PCI Express Root Ports */
/* TODO: This should not be done if a card is detected */
pci_or_config32(dev, 0x338, 1 << 26);
/* TODO: BWG specifies 50 ms timeout */
int n = 0;
do {
u32 reg32 = pci_read_config32(dev, 0x328);
n++;
if (((reg32 & 0xff000000) == 0x01000000) || (n > 50))
break;
udelay(100);
} while (1);
if (n > 50)
printk(BIOS_DEBUG, "%s: Timeout waiting for 328h\n",
dev_path(dev));
pci_or_config32(dev, 0x408, 1 << 27);
/* Disable this device if possible */
pch_disable_devfn(dev);
}