sb/intel/lynxpoint: Configure IOSF Port and Grant Count

Based on Wildcat Point and checked against version 1.9.1 of PCH
reference code. Note that this runs later in the init sequence,
compared to Wildcat Point, as it is easier to get the values of
the STRPFUSECFG registers this way.

Change-Id: I0fadd33d043e66c10d29dcf8ba9724723ad70a9b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91467
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/southbridge/intel/lynxpoint/pcie.c

@@ -132,6 +132,29 @@ static void update_num_ports(void)
 	       rpc.num_ports);
 }
 
+static u16 get_port_grant(u32 strpfusecfg)
+{
+	switch ((strpfusecfg >> 14) & 0x3) {
+	case 1: /* 2+1+1 */
+	case 3: /* 4 */
+		return 0x02;
+	case 2: /* 2+2 */
+		return 0x22;
+	case 0: /* 1+1+1+1 */
+	default:
+		return 0x00;
+	}
+}
+
+static void set_iosf_port_grant_count(void)
+{
+	u16 reg16 = get_port_grant(rpc.strpfusecfg1) << 0;
+	if (!pch_is_lp())
+		reg16 |= get_port_grant(rpc.strpfusecfg2) << 8;
+
+	RCBA16(0x103c) = reg16;
+}
+
 static void root_port_init_config(struct device *dev)
 {
 	int rp;
@@ -308,6 +331,9 @@ static void root_port_commit_config(void)
 	/* Perform clock gating configuration. */
 	pcie_enable_clock_gating();
 
+	/* 8.13 IOSF Port Configuration and Grant Count Programming */
+	set_iosf_port_grant_count();
+
 	for (i = 0; i < rpc.num_ports; i++) {
 		struct device *dev;