Currently, cse_request_reset() returns 0 if the reset type is
unsupported or CSE isn’t ready. This is the same as
CSE_TX_RX_SUCCESS, which makes failures impossible to detect.
Return CSE_TX_ERR_INPUT or CSE_TX_ERR_CSE_NOT_READY respectively,
so we can detect errors.
Change-Id: Idede7342157901946ba62ba6fcda6f304a4a3fd0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90272
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The MP Specification v1.4 says to program the spurious interrupt
in the following way:
"The APIC spurious interrupt must point to a vector whose lower
nibble is 0F, that is 0xF, where x is 0 - F. Here we use Int 00FH,
which handles spurious interrupts and supplies the necessary IRET.
This vector is assumed to have already been initialized in memory."
Follow the requirement and set the spurious interrupt vector
to 0x0F. This is what reference implementations, like EDK2, and also
BIOS vendors do.
Change-Id: I7bde413bbadca1de0079daf52b5501ba6638a4c3
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Halfway through the review of CB:89493 (commit 6e45016610 ("intel
soc,southbridge: Add Kconfig to set TSBS in IFD during build")) the
option was renamed and lost "CONFIG_" prefix in the Makefile. Add the
missing prefix.
The omission was discovered and the fix tested while trying to use this
option on Protectli VP6670 where incorrect Top Swap size prevented a
boot.
Adding a missing space while at it.
Change-Id: Ie85fc0b81b2231760878306cf065598bec390e9f
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90432
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Unlike other skywalker boards, GPIO14 is EN_PP6000_MIPI_DISP instead of
TCHSCR_REPORT_DISABLE on Padme. Therefore, in bootblock that GPIO should
be initialized low to meet the MIPI panel's required power-on sequence.
More precisely, IOVCC (LCD_VDDI) must lead AVDD by >2ms [1].
Add alias GPIO_EN_PP6000_MIPI_DISP to skywalker/gpio.h, and use it
instead of GPIO_TCHSCR_REPORT_DISABLE in the MIPI initialization code.
Also remove the EN_PP6000_MIPI_DISP pull-low in mipi_panel_power_on(),
as it has been pulled low in setup_chromeos_gpios().
[1] Preliminary+specification+TL121BVMS07+-00+V01+20250721.pdf
BUG=b:451746079
TEST=Boot Padme and confirm panel power-on timing is correct.
BRANCH=skywalker
Change-Id: I748a998cde35e58eac9eb590171b79864fc58ea9
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
This change introduces support for variant-specific firmware
configurations (fw_config) for the Rauru mainboard, specifically adding
initial support for the Sapphire variant.
The fw_config fields for Sapphire are defined in b:458266555.
All fw_config fields are now defined in variant-specific overridetree.cb
files (hylia, navi, rauru, sapphire). Consequently, access to these
fw_config values has been refactored to be encapsulated within
variant-specific fw_config.c files. This approach ensures that common
mainboard code does not need direct knowledge of variant-specific
fw_config definitions.
This is demonstrated by the audio amplifier initialization, which
now uses a variant-specific get_audio_amp_id() function to determine
the hardware present, rather than directly probing fw_config in the
common code.
BRANCH=None
BUG=b:458266555, b:448281461, b:461594346
TEST=emerge-tanjiro coreboot && emerge-rauru coreboot && test on navi
Change-Id: Iecca5820421f250e1a22cec110b36fb578edd9e7
Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90330
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Unify the I2C pad termination on all mc_ehl boards for better code
readability and continuity in the devicetrees. This patch does not
change the actual I2C pad termination configuration.
All the mc_ehl boards use external resistors for I2C termination.
Therefore, there is no need for internal termination at all. If the FSP
parameter 'SerialIoI2cPadsTermination' is omitted from the device tree,
the generic GPIO settings can define termination. If
'SerialIoI2cPadsTermination' is specified for an inactive I2C
controller, those settings are ignored.
This patch consistently adds 'SerialIoI2cPadsTermination' to the device
tree for all active mc_ehl boards, and removes it for controllers that
are switched off.
This topic came up in review for commit 864e3ca661
("mb/siemens/mc_ehl6: Adjust I2C setup").
TEST=Build and boot to OS on mc_ehl1/2/4 and compare register contents
of PAD_CFG_DW0/1 registers for all 8 I2C controllers before and after
the patch to ensure no change in I2C pad termination.
Change-Id: Iba75778893e0b6a7acb68535d0407dc1fc43d2ca
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Generate RAM ID for MT62F512M32D1DS-023 WT:E
DRAM Part Name ID to assign
MT62F1G32D2DS-031RF WT:C 4 (0100)
BUG=b:466889567
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I6a6ed45cacc9a10bc7a2cfc3b41cee93c552a6cd
Signed-off-by: Wayby Zhai <wayby.zhai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90411
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix the bit definition for RGS_AUX_LDO_EN_READY_MASK in the MT8189
dptx_reg.h file, changing it from BIT(2) to BIT(0). The MT8189 is only
polling BIT(0) status instead of BIT(2). This correction ensures proper
functionality of the AUX LDO readiness check.
BUG=b:461384417
TEST=Boot up can see develop mode.
BRANCH=skywalker
Signed-off-by: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Change-Id: Id4a85c619311fecde5bc84ad29c521b7d20ffdd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90362
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current code doesn't make much sense. The offset created by the
skipping of NOP tokens is just ignored.
Reorder the lines to skip the NOP tokens first.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I860a57e4a773b634149e84271b8322d78ac20e32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The option was introduced by
commit ae738acdc5 ("cpu/x86: Support CPUs without rdmsr/wrmsr")
for the intel quark SOC. However the SOC doesn't exist anymore in
coreboot. Nor does any other SOC use this option.
Therefore remove it.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I4f3f5e91c00784c159042271387c2e862f351881
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90421
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use is_dev_enabled() on devicetree device to enable/disable USB4 devices
by updating the corresponding FSP UPDs.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: If0ae88eaaf88954159b55fdf030eb96d74ee29f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Glinda and Faegan are closely related and there's only very minimal
difference from the coreboot viewpoint, so Feagan is added as Glianda
variant and not as a new SoC folder. Faegan has a different CPUID, so
it's added to the CPU table, and some GPIO muxes have a few more valid
settings to route the MDIO pins related to the 2 XGBE controllers to
GPIO pins.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I57699089a4a3ac7ddb037f254d42cb043b816c55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90417
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some specific Glinda SoCs support dual 10G PCI ethernet devices.
Add defines and chipset entries for XGBE0 and XGBE1.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7e3bb1819165a7c2f4284b76450f831bb99b1ad3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90416
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Glinda actually supports warm reset, so we don't need to toggle the
PwrGood for all resets.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I70e9a13b84219847795e65b39c52114592a2cb61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90415
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fill in the DIMM voltages as reported by FSP.
Change-Id: I22d6bac93d8e8b8130f89a440be661829c700fe9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
There is ESPI1 fixed resource living 64K above the ESPI0 fixed
resource. Report it if the hardware has ESPI1 bus.
Change-Id: I7245850450cfa9de326f26c83c4f01c8d167f8be
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
On systems with AMD ROM armor enabled the SPI base address register
in LPC bridge PCI device space is not accessible (returns all FFs).
In such case the AML code will not be able to retrieve the SPI BAR
and report it properly. Use fixed bases instead to avoid running
into this problem in the future.
Change-Id: Ia01508e5ddf2da053f9bf4116c5e05b89500f772
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89488
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the dsc_config parameter to mtk_ddp_soc_mode_set to support DSC
configuration, and updated function calls to pass dsc_config from
panel_serializable_data. The MIPI_DSI_DUAL_CHANNEL flag is set when the
panel uses the dual MIPI path. This patch is prepared for upcoming MIPI
DSI and DSC changes.
BUG=b:424782827
TEST=Build pass.
Change-Id: Ia3ada4aca41a231adb2273c34deef636889c5c81
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90377
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Refactor the MIPI DPHY implementation to improve modularity and
maintainability:
- Extract the dphy timing calculation to mtk_mipi_dphy_v1.c.
- Update Makefiles for multiple chips to include the new file.
- Enhance board-specific tuning by isolating timing configuration logic.
BUG=b:424782827
TEST=Build pass, boot ok, display ok
Change-Id: Ie0daa6e7b384a172ed483eda926e5acd1e3c539a
Signed-off-by: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90358
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable Unified Firmware and Secondary Source Configuration (UFSC)
support for Matsu.
UFSC standardizes the bitfields and bitmap definitions for firmware
configuration. Update overridetree.cb with new UFSC definitions and
enable EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC.
BUG=b:454549696,b:444322626
TEST=Ensure the probed fw_config matches the written configuration.
BRANCH=none
Change-Id: I55e2b9fd17290731f365632d92f1b26923c8022a
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90299
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SSDT contains:
CreateByteField (PPOP, Local0, TPPF)
However, CreateByteField requires the source argument to be
(Buffer | String | Integer). PPOP is an OperationRegion, so
iasl correctly reports:
Error 6058 - Invalid type ([Region] found)
Per ACPI spec, OperationRegions must use CreateField rather than
CreateByteField. Replace the AML emission with:
CreateField (PPOP, Local0 * 8, 8, TPPF)
This reads one byte at an arbitrary offset inside the PPI
OpRegion and is fully standards-compliant. This isn't a
functional change, just "correct".
Test=boot starbook_mtl, verify iasl can decompile and recompile
SSDT and TPM is still operational.
Change-Id: If80bb5bf69562f8b904c1b315e95a0b5627efbc4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Based on the Unified Firmware and Second Source Configuration(UFSC)
Developer's Guide to generate the UFSC firmware config file
ruby_ap_fw_config.cb and copy the content to overridetree.cb.
https://chromium.googlesource.com/chromiumos/config/+/refs/heads/main/
util/ufsc/ufsc_developer_guide.md
BUG=b:460231264
TEST=util/abuild/abuild -x -t GOOGLE_RUBY -a
BRANCH=none
Change-Id: Ia9536ba9b11ca83e80e7e6b3042a04fc6cdbf526
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90375
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch enables Cirrus Audio codec and HDA in devicetree for ojal
and updates FW config for GPIO's according to schematics revision 0.9.
RDC kit no:840138
Scope (\_SB.PCI0.HDAS.SNDW)
{
Device (SW30)
{
Name (_ADR, 0x00033001FA424301) // _ADR: Address
Name (_DDN, "Headset Codec") // _DDN: DOS Device Name
Name (_SUB, "1337") // _SUB: Subsystem ID
...
BUG=b:437459757
TEST=Build ojal board and check SSDT tables for codec.
Change-Id: Id4110263750ef5ff2375199d073175b47dc4f909
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bhat D, Krishna P <krishna.p.bhat.d@intel.com>
Modify ocicat TPM_TIS_ACPI_INTERRUPT to fix TPM timeout
BUG=b:457879750
TEST=flash and boot to DUT, verify can boot to OS.
Change-Id: Ie6f35c8c68b8e5849a038124739f9ec4846f4aef
Signed-off-by: lai.kaiden <lai.kaiden@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90359
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds wake functionality to the CNVi Bluetooth device by
registering to "GPE0_PME_B0" using the common CNVi block.
BUG=454341255
TEST=Able to wake up the device from a low power state using a keyboard
Bluetooth device.
Change-Id: I5a0bbd0523611e8e38b62f8b3fdf77f736d3136f
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90379
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Upadhyay, Varun <varun.upadhyay@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Running FWTS detected a problem with FACS having non-zero
values in reserved fields:
FAILED [MEDIUM] FACSReservedNonZero: Test 1, FACS Reserved field must be zero,
got 0x00fe7bcd instead
FAILED [HIGH] FACSReservedBitsNonZero: Test 1, FACS OSPM Flags Bits [31..1] must
be zero, got 0xf23bcdd8 instead
FAILED [LOW] FACSInvalidReserved1: Test 1, FACS: 2nd Reserved field is non-zero
Clear whole FACS table and then start filling the non-zero values to
fix the issue.
TEST=Run FWTS V25.01.00 on Gigabyte MZ33-AR1 and see no error for FACS
test.
Change-Id: I2af4caea155e3707e3b7832824e81e6b69f836a5
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89923
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change below GPIO pins status to fix audio function.
GPP_D10 : Native function 2
GPP_D11 : Native function 2
GPP_D12 : Native function 2
GPP_D13 : Native function 2
BUG=b:466263099
TEST=Build and boot to OS, check soundcard shows using command
'cat /proc/asound/cards' and check audio jack and amp are work.
Change-Id: Ieac732ebf5149a13fe7aba36bf14627ded4783ad
Signed-off-by: luca.lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90394
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This update enhances the Intel touch driver by incorporating support for
newly added _DSD entries specific to I2C devices. The enhancements
include:
- Adding new entries in the I2C _DSD to enable configurations for
maximum frame size and interrupt delay settings.
- Introducing device-specific interrupt delay settings tailored for
Hynitron devices.
These changes ensure improved configurability and performance tuning for
supported devices. It is crucial to use this update with an operating
system that includes corresponding changes for this new support.
ATTENTION: This change requires a THC driver fix. If the OS does not
have the driver fix, please use LPSS I2C or disable the touchscreen
and touchpad. For instance, on the Google Fatcat board, use the
following CBI fw_config options:
TOUCHSCREEN field: TOUCHSCREEN_LPSS_I2C or TOUCHSCREEN_NONE
TOUCHPAD field: TOUCHPAD_LPSS_I2C or TOUCHPAD_NONE
BUG=none
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Iaab8329c97247161395d203a5efa92c053acb3a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89214
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kim, Kyoung Il <kyoung.il.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Parse the supported voltages from the DDR3 SPD and populate the
corresponding fields in CBMEM_ID_MEMINFO to make sure the SMBIOS
type 17 tables report the actual supported voltages of the DIMM.
Change-Id: I35af7c23f285af10b607a80eab7f4d9df664b3fd
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Some silcon initialization modules may provide more detailed
information about the DIMMs, like type details or voltages.
Extend the memory_info structure with type_detail and max/min
voltage. Use the new fields when producing SMBIOS tables if their
value is non-zero. Otherwise, keep previous behavior.
Change-Id: I01ae8ea1f5a8fec53e151c040d893376c3d23be2
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89483
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for the new memory Micron MT62F1G32D2DS-031RF WT:C using
spd-3.hex.
DRAM Part Name ID to assign
H9JCNNNBK3MLYR-N6E 0 (0000)
K3KL6L60GM-MGCT 1 (0001)
K3KL8L80CM-MGCT 2 (0010)
MT62F1G32D2DS-026 WT:B 2 (0010)
H58G56CK8BX146 3 (0011)
MT62F1G32D2DS-031RF WT:C 4 (0100)
BUG=b:459934066
BRANCH=firmware-trulo-15217.771.B
TEST=util/spd_tools/bin/part_id_gen ADL lp5 \
src/mainboard/google/brya/variants/uldrenite/memory \
src/mainboard/google/brya/variants/uldrenite/memory/mem_parts_used.txt
Change-Id: I76d8e1de2b96bd5f2cb319056d1f9307a7e2a114
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90255
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Update the logic to properly condition the slow battery charging feature.
Previously, enable_slow_battery_charging() was called solely if the
system was in a low-power boot state (is_low_power_boot()).
This commit adds an explicit check for
`google_chromeec_is_charger_present()` to ensure that the slow charging
feature is only enabled when a charger is physically connected.
TEST=Able to build and boot google/quenbi.
Change-Id: I24b6626343a25a4fab3f5d77c1d114e797781be7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The google_chromeec_is_charger_present function previously relied on
executing the EC_CMD_BATTERY_DYNAMIC_INFO command to check the
EC_BATT_FLAG_AC_PRESENT flag.
This commit refactors the function to directly read the host event
register (EC events B) and check for the EC_HOST_EVENT_AC_CONNECTED
event flag instead.
This approach is much more efficient as it avoids the overhead of
sending and receiving a full EC command (savings ~25-30ms), using a
readily available cached status instead.
TEST=Able to build and boot google/quenbi.
Change-Id: I2ec9aca5991394ed1d4998da37e074e9324bd672
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90334
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add support for MIPI panel on Sapphire and enable NS130069-M00 as
the default panel. The panel uses TPS65132S as the bias IC, with supply
set to ±5.9V. Add TPS65132S initialization and power-on sequence are
configured according to the specification.
BUG=b:456907241, b:448281461
TEST=Check display initialization log and display are normal
BRANCH=none
Change-Id: I755b63725fe6243a45deff04e8b2fb10162d5f44
Signed-off-by: Xiaokun Qiao <qiaoxiaokun@huaqin.corp-partner.google.com>
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Add the support RAM parts for gothrax.
Here is the ram part number list:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H58G56AK6BX069 1 (0001)
K3LKBKB0BM-MGCP 2 (0010)
H9JCNNNBK3MLYR-N6E 0 (0000)
H9JCNNNCP3MLYR-N6E 3 (0011)
K3KL8L80CM-MGCT 4 (0100)
BUG=b:463859361
BRANCH=None
TEST=emerge-nissa coreboot
Change-Id: Ia43d300e63d22df27d5632d702a404a18442ea75
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90239
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Ramdump is a debug image loaded during a crash to capture memory
contents for post-crash analysis. This patch adds support for
loading this image during the qclib_rerun() sequence.
Key changes:
1) Introduce QC_RAMDUMP_ENABLE Kconfig option to control ramdump image
loading.
2) Add qclib_check_dload_mode() as a weak function that works in
conjunction with the Kconfig check to decide whether the ramdump
image should be loaded.
3) Add new CBFS file entry and table entry definition for ramdump_meta.
4) Re-use "apdp_ramdump_meta" region for ramdump metadata storage.
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: I42bcd74c3d236a6af49ec4b548bc9cda33bd0825
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90306
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds build rules for packing the APDP image in CBFS.
It also updates the memory layout to include a dedicated region
for APDP metadata storage (4KB at 0x14890000).
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: Ia3093ef6619dd504c829cf6ba6f672f16070f68a
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch introduces a new Kconfig option, QC_APDP_ENABLE, to control
Application Processor Debug Policy (APDP) image loading. When this
option is enabled, the APDP image is loaded during the
qclib_load_and_run() sequence. It also adds a new CBFS file entry and
table entry definition for apdp_meta, along with a memory region symbol
apdp_ramdump_meta for metadata storage.
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: I8d0847c99a1129359f2c758b7a07b9c022f1c8c8
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90303
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change ensures that the display is always enabled for the Google
Bluey mainboard as firmware splash screen is POR for this device..
This change helps to avoid an additional reset while doing EC sync
operation by payload.
BUG=none
BRANCH=none
TEST=Able to avoid one additional resets during EC SW sync.
Change-Id: If1d8788cbbd72d6bc4397b1b7160e9f4669716db
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The value 0 passed as the reboot_flags argument to
google_chromeec_reboot is now explicitly defined as
EC_REBOOT_FLAG_IMMEDIATE in ec_commands.h.
Update calls to google_chromeec_reboot with EC_REBOOT_COLD to use the
new flag for clarity and to ensure the intended EC-based reboot is
performed.
This change doesn't introduce anything new, so there's no change
in behavior.
Change-Id: I6701c94101c5085cfcc7fbf2e614c4f23d843225
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The current read calibration data flow may cause memory overwrite due to
struct size mismatch, resulting in fast calibration flow failure. Need
to align the struct for storing DRAM calibration data between coreboot
and mtk-dramk repo to prevent memory overwrite.
BUG=b:450724525
TEST=Bootup ok.
Change-Id: Ic59bc9c7f12c454702ba894dea5dce94984e2121
Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90354
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: jason-ch chen <Jason-ch.Chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On AMD non-car system the bootblock is integrated into PSP directories
and copied to host DRAM before reset vector. coreboot knows the exact
DRAM range where the bootblock will be copied to based on
CONFIG_ROMSTAGE_ADDR and CONFIG_C_ENV_BOOTBLOCK_SIZE. The code only
needs to check the exact coreboot program size using linker symbols
measure the right memory range.
Based on the Apollo Lake tspi_soc_measure_bootblock, create an
equivalent implementation for AMD platforms using mem_region_device.
TEST=Bootblock is measured properly on Gigabyte MZ33-AR1 when measured
boot is enabled and CRTM initialization no longer fails.
Change-Id: I163e6b0ef0313e7dbb66ba5b07c35724a14276aa
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89145
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
More complex systems, such as servers, may have scarse space below 4G
for MMIO. With multiple root bridges needing some 32bit MMIO space it
becomes very hard to squeeze all resources. Allow to set 64bit ECAM
MMCONF base address in the MSR to free some space in the 32bit address
space. Of course using 64bit ECAM MMCONF requires the use of x86_64
mode and a proper amount of address space to be mapped with page
tables.
TEST=Set ECAM MMCONF to 0x3ffb00000000 on Gigabyte MZ33-AR1 and observe
the PCI access works in the console output.
Change-Id: I80e5a1bed33e12aa089355df64cc29887acc27f2
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89112
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The breaks for `if` and `else` are inconsistent; remove all breaks for
these.
Change-Id: Ie76f38387fd5ef330b432c0462cb1101571c73db
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90286
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
