3053cd2dad
On systems with AMD ROM armor enabled the SPI base address register in LPC bridge PCI device space is not accessible (returns all FFs). In such case the AML code will not be able to retrieve the SPI BAR and report it properly. Use fixed bases instead to avoid running into this problem in the future. Change-Id: Ia01508e5ddf2da053f9bf4116c5e05b89500f772 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89488 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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| .. | ||
| acpi | ||
| arch | ||
| commonlib | ||
| console | ||
| cpu | ||
| device | ||
| drivers | ||
| ec | ||
| include | ||
| lib | ||
| mainboard | ||
| northbridge | ||
| sbom | ||
| security | ||
| soc | ||
| southbridge | ||
| superio | ||
| vendorcode | ||
| Kconfig | ||